Lines Matching full:disabled

47 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
54 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
61 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
71 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
78 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
85 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
102 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
118 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
131 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
141 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
160 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
169 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
176 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
223 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
236 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
245 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
252 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
259 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
269 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
276 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
283 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
302 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
320 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
333 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
340 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
347 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
354 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
364 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
371 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
378 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
385 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
484 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
491 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
501 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
508 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
518 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
2072 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
2117 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
2124 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
2131 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
2138 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
2145 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
2155 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
2162 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
2169 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
2176 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
2183 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
2211 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
2221 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
2234 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
2240 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
2246 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
2252 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
2258 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
2267 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
2274 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
2281 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
2288 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
2298 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
2305 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
2312 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
2319 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
2338 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
2396 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
2538 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
2545 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
2552 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
2559 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
2566 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
2573 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
2580 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
2587 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
2594 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
2601 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
2608 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
2615 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
2622 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
2629 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
2636 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
2643 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
2650 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
2657 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
2664 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
2671 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
2678 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
2685 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
2692 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
2699 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
2706 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
2713 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
2720 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
2727 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
2734 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
2741 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
2748 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
2755 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
2765 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
2772 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
2779 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
2786 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
2793 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
2800 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
2807 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
2814 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
2821 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
2828 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
2835 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
2842 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
2849 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
2856 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
2863 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
2870 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
2877 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
2884 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
2891 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
2898 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
2905 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
2912 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
2919 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
2926 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
2933 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
2940 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
2947 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
2954 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
2961 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
2968 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
2975 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
2982 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
2993 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
3054 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
3064 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
3162 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
3205 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
3241 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
3269 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
3275 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
3281 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
3287 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
3293 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
3299 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
3305 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
3311 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
3317 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
3323 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
3329 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
3335 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
3341 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
3347 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
3353 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
3359 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
3365 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
3371 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
3377 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
3383 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
3389 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
3395 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
3401 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
3407 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
3413 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
3419 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
3425 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
3431 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
3440 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
3447 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
3454 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
3461 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
3468 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
3475 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
3482 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
3489 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
3496 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
3503 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
3510 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
3517 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
3524 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
3531 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
3538 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
3545 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
3552 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
3559 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
3566 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
3573 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
3580 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
3587 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
3594 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
3601 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
3608 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
3615 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
3622 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
3629 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
3639 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
3646 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
3653 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
3660 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
3667 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
3674 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
3681 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
3688 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
3695 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
3702 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
3709 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
3716 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
3723 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
3730 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
3737 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
3744 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
3751 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
3758 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
3765 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
3772 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
3779 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
3786 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
3793 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
3800 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
3807 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
3814 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
3821 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
3828 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
4013 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
4019 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
4028 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
4035 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
4042 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
4052 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
4059 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
4066 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
4076 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
4131 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
4161 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
4171 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
4174 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
4180 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
4186 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
4192 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
4195 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
4198 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
4201 /* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
4204 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
4210 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
4216 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
4225 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
4232 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
4239 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
4246 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
4250 /* Bit 4 : Enable interrupt on DISABLED event. */
4251 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
4252 …IO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
4253 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
4260 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
4267 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
4274 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
4281 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
4291 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
4298 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
4305 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
4312 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
4316 /* Bit 4 : Disable interrupt on DISABLED event. */
4317 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
4318 …IO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
4319 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
4326 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
4333 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
4340 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
4347 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
4435 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
4507 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
4513 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
4519 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
4525 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
4531 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
4537 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
4543 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
4549 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
4564 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
4589 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
4595 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
4618 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
4680 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
4686 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
4692 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
4698 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
4704 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
4710 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
4716 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
4722 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
4759 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
4772 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
4785 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
4794 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
4804 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
4814 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
4830 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
4843 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
4850 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
4857 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
4864 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
4871 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
4878 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
4888 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
4895 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
4902 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
4909 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
4916 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
4923 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
4933 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
4939 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
4945 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
4951 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
4957 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
4963 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
4972 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
4979 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
4986 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
4993 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
5000 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
5007 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
5017 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
5024 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
5031 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
5038 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
5045 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
5052 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
5083 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
5096 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
5106 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
5116 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
5174 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
5187 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
5196 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
5203 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
5210 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
5220 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
5227 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
5234 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
5272 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
5344 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
5357 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
5367 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
5377 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
5390 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
5396 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
5402 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
5408 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
5414 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
5420 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
5426 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
5432 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
5441 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
5448 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
5455 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
5462 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
5472 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
5479 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
5486 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
5493 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
5530 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
5543 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
5549 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
5558 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
5565 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
5572 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
5579 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
5586 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
5593 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
5603 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
5610 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
5617 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
5624 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
5631 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
5638 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
5672 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
5712 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
5725 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
5731 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
5740 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
5747 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
5754 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
5761 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
5768 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
5775 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
5785 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
5792 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
5799 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
5806 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
5813 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
5820 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
5861 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
5915 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
5924 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
5938 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
5944 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
5972 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
5982 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
6052 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
6058 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
6064 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
6070 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
6076 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
6082 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
6088 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
6094 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
6126 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */