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/nrf52832-nimble/rt-thread/components/drivers/mtd/
H A Dmtdnand.c14 #define NOTALIGNED(x) ((x & (chip->page_size - 1)) != 0)
19 static uint8_t *nand_fill_oob(rt_nand_t *chip, uint8_t *oob, size_t len, struct mtd_io_desc *desc) in nand_fill_oob() argument
21 rt_memset(chip->oob_poi, 0xff, chip->oobsize); in nand_fill_oob()
27 rt_memcpy(chip->oob_poi + desc->ooboffs, oob, len); in nand_fill_oob()
32 const struct mtd_oob_region *free = chip->freelayout; in nand_fill_oob()
39 rt_memcpy(chip->oob_poi + boffs, oob, bytes); in nand_fill_oob()
49 static uint8_t *nand_transfer_oob(rt_nand_t *chip, uint8_t *oob, struct mtd_io_desc *desc, size_t l… in nand_transfer_oob() argument
55 rt_memcpy(oob, chip->oob_poi + desc->ooboffs, len); in nand_transfer_oob()
60 struct mtd_oob_region *free = (struct mtd_oob_region *)chip->freelayout; in nand_transfer_oob()
84 rt_memcpy(oob, chip->oob_poi + boffs, bytes); in nand_transfer_oob()
[all …]
/nrf52832-nimble/rt-thread/components/dfs/filesystems/uffs/src/example/
H A Dflash-interface-example.c74 #define CHIP_SET_CLE(chip) { chip = chip; } argument
75 #define CHIP_CLR_CLE(chip) {} argument
76 #define CHIP_SET_ALE(chip) {} argument
77 #define CHIP_CLR_ALE(chip) {} argument
78 #define CHIP_SET_NCS(chip) {} argument
79 #define CHIP_CLR_NCS(chip) {} argument
80 #define CHIP_BUSY(chip) {} argument
81 #define CHIP_READY(chip) {} argument
82 #define WRITE_COMMAND(chip, cmd) {} argument
83 #define WRITE_DATA_ADDR(chip, block, page, offset) {} argument
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/nrf52832-nimble/rt-thread/components/drivers/spi/sfud/src/
H A Dsfud.c45 /* supported flash chip information table */
61 /* QSPI flash chip's extended information table */
169 if (flash->chip.capacity <= 0x1000000) { in qspi_set_read_cmd_format()
207 if ((qspi_flash_ext_info_table[i].mf_id == flash->chip.mf_id) in sfud_qspi_fast_read_enable()
208 && (qspi_flash_ext_info_table[i].type_id == flash->chip.type_id) in sfud_qspi_fast_read_enable()
209 && (qspi_flash_ext_info_table[i].capacity_id == flash->chip.capacity_id)) { in sfud_qspi_fast_read_enable()
266 …/* if the user don't configure flash chip information then using SFDP parameter or static flash pa… in hardware_init()
267 if (flash->chip.capacity == 0 || flash->chip.write_mode == 0 || flash->chip.erase_gran == 0 in hardware_init()
268 || flash->chip.erase_gran_cmd == 0) { in hardware_init()
279 flash->chip.name = NULL; in hardware_init()
[all …]
/nrf52832-nimble/rt-thread/components/drivers/include/drivers/
H A Dmtdnand.h24 … NAND_CMD_PAGE_RD, /* read data to chip's page buffer,do WaitBusy after this cmd in low driver */
25 NAND_CMD_PAGE_WR0, /* write data to chip's page buffer */
61 void (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code);
63 int(*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc);
85 int(*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
86 int(*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page);
93 …int(*read_buf)(rt_nand_t *nand, uint8_t *buf, int len); /* read data from nand chip's page …
94 …int(*write_buf)(rt_nand_t *nand, const uint8_t *buf, int len);/* write data to nand chip's page b…
H A Di2c.h22 #define RT_I2C_ADDR_10BIT (1u << 2) /* this is a ten bit chip address */
/nrf52832-nimble/rt-thread/documentation/doxygen/
H A Dhardware.h8 * @brief Hardware Related Package includes board support package(BSP) and CSP(Chip
15 * Chip Support Package (CSP) is a software set that contains chip specific software.
17 * chip. In RT-Thread RTOS, the csp is placed under libcpu directory.
/nrf52832-nimble/rt-thread/components/drivers/spi/
H A Dspi_flash_sfud.c381 rtt_dev->geometry.sector_count = sfud_dev->chip.capacity / sfud_dev->chip.erase_gran; in rt_sfud_flash_probe()
382 rtt_dev->geometry.bytes_per_sector = sfud_dev->chip.erase_gran; in rt_sfud_flash_probe()
383 rtt_dev->geometry.block_size = sfud_dev->chip.erase_gran; in rt_sfud_flash_probe()
387 qspi_cfg.medium_size = sfud_dev->chip.capacity; in rt_sfud_flash_probe()
511 …INDEX] = "sf bench - full chip benchmark. DANGER: It will erase full ch… in sf()
542 if (sfud_dev->chip.capacity < 1024 * 1024) { in sf()
543 …rt_kprintf("%d KB %s is current selected device.\n", sfud_dev->chip.capacity / 1024, sfud_dev->nam… in sf()
545 … rt_kprintf("%d MB %s is current selected device.\n", sfud_dev->chip.capacity / 1024 / 1024, in sf()
644 rt_kprintf("DANGER: It will erase full chip! Please run 'sf bench yes'.\n"); in sf()
647 /* full chip benchmark test */ in sf()
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/nrf52832-nimble/rt-thread/components/drivers/spi/sfud/inc/
H A Dsfud_flash_def.h55 /* flash chip information */
57 char *name; /**< flash chip name */
68 /* QSPI flash chip's extended information compared with SPI flash */
73 uint8_t read_mode; /**< supported read mode on this qspi flash chip */
117 /* SFUD supported flash chip information table. If the flash not support JEDEC JESD216 standard,
118 …* then the SFUD will find the flash chip information by this table. You can add other flash to her…
H A Dsfud_def.h272 sfud_flash_chip chip; /**< flash chip information */ member
H A Dsfud_cfg.h56 …* Using probe flash JEDEC ID then query defined supported flash chip information table. @see SFUD_…
/nrf52832-nimble/nordic/nrfx/drivers/src/
H A Dnrfx_nfct.c128 …brief Internal auxiliary function for checking whether the program is running on the NRF52840 chip.
130 * @retval true It is NRF52480 chip.
131 * @retval false It is an other chip.
141 * the nRF52840 chip.
143 * @retval true It is the nRF52480 chip and it is the first sample version.
144 * @retval false It is an other chip.
155 * the nRF52840 chip.
157 * @retval true It is the nRF52480 chip and it is the final version.
158 * @retval false It is an other chip.
169 bool eng_a; /**< Engineering sample A of the NRF52840 chip. */
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/nrf52832-nimble/nordic/nrfx/drivers/include/
H A Dnrfx_nfct.h337 * If you are using the nRF52832 chip, the workarounds for the following anomalies are applied:
345 …* If you are using the nRF52840 chip, rev. Engineering A, the workarounds for the following anomal…
351 …* If you are using the nRF52840 chip, rev. 1, or rev. Engineering B or C, the workarounds for the …
358 …* The application of the implemented workarounds for the nRF52840 chip is determined at runtime an…
359 * on the chip variant.
H A Dnrfx_qspi.h202 * @brief Function for starting erasing of one memory block - 4KB, 64KB, or the whole chip.
216 * @param[in] start_address Memory address to start erasing. If chip erase is performed, address
227 * @brief Function for starting an erase operation of the whole chip.
/nrf52832-nimble/rt-thread/documentation/
H A Dcoding_style_en.txt13 have descriptive names. For example, the port of a chip should be composed of
14 the name of the chip and the category of the chip. Directories under components/
/nrf52832-nimble/rt-thread/libcpu/arm/s3c44b0/
H A Dstart_rvds.S231 ;// <o0.6..7> Toch: Chip Select Hold on nOE
236 ;// <o0.11..12> Tcos: Chip Select Set-up nOE
257 ;// <o1.6..7> Toch: Chip Select Hold on nOE
262 ;// <o1.11..12> Tcos: Chip Select Set-up nOE
283 ;// <o2.6..7> Toch: Chip Select Hold on nOE
288 ;// <o2.11..12> Tcos: Chip Select Set-up nOE
309 ;// <o3.6..7> Toch: Chip Select Hold on nOE
314 ;// <o3.11..12> Tcos: Chip Select Set-up nOE
335 ;// <o4.6..7> Toch: Chip Select Hold on nOE
340 ;// <o4.11..12> Tcos: Chip Select Set-up nOE
[all …]
/nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/include/asm/
H A Dppc405.h142 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
143 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
471 #define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
472 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
473 #define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
721 * On Chip Memory
935 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
936 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
937 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
938 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/s3c24x0/
H A Dstart_rvds.S32 ; * from execution address to on-chip RAM.
276 ;// <o2.11..12> Tcos: Chip Selection Set-up Time before nOE
281 ;// <o2.6..7> Tcoh: Chip Selection Hold Time after nOE
293 ;// <o3.11..12> Tcos: Chip Selection Set-up Time before nOE
298 ;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE
310 ;// <o4.11..12> Tcos: Chip Selection Set-up Time before nOE
315 ;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE
327 ;// <o5.11..12> Tcos: Chip Selection Set-up Time before nOE
332 ;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE
344 ;// <o6.11..12> Tcos: Chip Selection Set-up Time before nOE
[all …]
/nrf52832-nimble/rt-thread/components/drivers/spi/sfud/
H A DREADME.md68 …def.h`。每个 SPI Flash 会对应一个该结构体，该结构体指针下面统称为 Flash 设备对象。初始化成功后在 `sfud_flash->chip` 结构体中会存放 SPI Flash …
134 > 注意：擦除操作将会按照 Flash 芯片的擦除粒度（详见 Flash 数据手册，一般为 block 大小。初始化完成后，可以通过 `sfud_flash->chip.erase_gran` 查看…
171 > 注意：擦除操作将会按照 Flash 芯片的擦除粒度（详见 Flash 数据手册，一般为 block 大小。初始化完成后，可以通过 `sfud_flash->chip.erase_gran` 查看…
237 ….chip = { "W25Q64FV", SFUD_MF_ID_WINBOND, 0x40, 0x17, 8L * 1024L * 1024L, SFUD_WM_PAGE_256B, 4096,…
/nrf52832-nimble/rt-thread/libcpu/arm/lpc24xx/
H A Dstart_rvds.S35 ; * from on-chip Flash to on-chip RAM.
48 ; * from on-chip RAM starting at address 0x40000000.
778 ;// <o0.6> PC: Chip select polarity
779 ;// <0=> Active LOW chip select
780 ;// <1=> Active HIGH chip select
845 ;// <o0.6> PC: Chip select polarity
846 ;// <0=> Active LOW chip select
847 ;// <1=> Active HIGH chip select
912 ;// <o0.6> PC: Chip select polarity
913 ;// <0=> Active LOW chip select
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/AT91SAM7X/
H A Dstart_rvds.S20 ; * on-chip RAM to address 0.
23 ; * from on-chip Flash to on-chip RAM.
350 ; Remap on-chip RAM to address 0
/nrf52832-nimble/rt-thread/libcpu/arm/AT91SAM7S/
H A Dstart_rvds.S20 ; * on-chip RAM to address 0.
23 ; * from on-chip Flash to on-chip RAM.
347 ; Remap on-chip RAM to address 0
/nrf52832-nimble/packages/NimBLE-latest/nimble/drivers/native/src/
H A Dble_phy.c455 * the chip limits, we "rail" the power level so we dont exceed the min/max
456 * chip values.
592 * phy. For this chip, if encryption is enabled, the maximum payload is 27
/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/include/controller/
H A Dble_ll_conn.h139 * tx_phy_mode: chip specific phy mode for tx
140 * rx_phy_mode: chip specific phy mode for rx
/nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/include/
H A Dconfig.h49 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
/nrf52832-nimble/nordic/nrfx/hal/
H A Dnrf_nvmc.h49 * of the chip. In order to write to NVM the controller must be powered

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