Lines Matching full:chip
142 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
143 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
471 #define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
472 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
473 #define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
721 * On Chip Memory
935 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
936 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
937 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
938 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
939 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
940 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
941 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */