1*10465441SEvalZero #ifndef __CONFIG_H 2*10465441SEvalZero #define __CONFIG_H 3*10465441SEvalZero 4*10465441SEvalZero #define CONFIG_405EP 1 /* this is a PPC405 CPU */ 5*10465441SEvalZero #define CONFIG_4xx 1 /* member of PPC4xx family */ 6*10465441SEvalZero 7*10465441SEvalZero #define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ 8*10465441SEvalZero #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ 9*10465441SEvalZero 10*10465441SEvalZero #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 11*10465441SEvalZero #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 12*10465441SEvalZero #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 13*10465441SEvalZero 14*10465441SEvalZero #define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ 15*10465441SEvalZero #define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */ 16*10465441SEvalZero #define CONFIG_SYS_HZ 100 17*10465441SEvalZero #define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) 18*10465441SEvalZero 19*10465441SEvalZero /* 20*10465441SEvalZero * UART 21*10465441SEvalZero */ 22*10465441SEvalZero #define CONFIG_BAUDRATE 115200 23*10465441SEvalZero #define CONFIG_SERIAL_MULTI 24*10465441SEvalZero #define CONFIG_SYS_BAUDRATE_TABLE \ 25*10465441SEvalZero {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 26*10465441SEvalZero 27*10465441SEvalZero /* 28*10465441SEvalZero * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. 29*10465441SEvalZero * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. 30*10465441SEvalZero * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. 31*10465441SEvalZero * The Linux BASE_BAUD define should match this configuration. 32*10465441SEvalZero * baseBaud = cpuClock/(uartDivisor*16) 33*10465441SEvalZero * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, 34*10465441SEvalZero * set Linux BASE_BAUD to 403200. 35*10465441SEvalZero */ 36*10465441SEvalZero #define CONFIG_SYS_BASE_BAUD 691200 37*10465441SEvalZero #define CONFIG_UART1_CONSOLE 1 38*10465441SEvalZero 39*10465441SEvalZero /*----------------------------------------------------------------------- 40*10465441SEvalZero * Start addresses for the final memory configuration 41*10465441SEvalZero * (Set up by the startup code) 42*10465441SEvalZero */ 43*10465441SEvalZero #define CONFIG_SYS_FLASH_BASE 0xFFE00000 44*10465441SEvalZero 45*10465441SEvalZero /*----------------------------------------------------------------------- 46*10465441SEvalZero * FLASH organization 47*10465441SEvalZero */ 48*10465441SEvalZero #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 49*10465441SEvalZero #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 50*10465441SEvalZero 51*10465441SEvalZero #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 52*10465441SEvalZero #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 53*10465441SEvalZero 54*10465441SEvalZero #define CONFIG_SYS_FLASH_ADDR0 0x555 55*10465441SEvalZero #define CONFIG_SYS_FLASH_ADDR1 0x2aa 56*10465441SEvalZero #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short 57*10465441SEvalZero 58*10465441SEvalZero #endif /* __CONFIG_H */ 59