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/nrf52832-nimble/rt-thread/libcpu/mips/common/
H A Dmips_context.h30 #define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */
55 sw k0, (29 * 4)(sp)
58 sw $0, ( 0 * 4)(sp)
59 sw $1, ( 1 * 4)(sp)
60 sw $2, ( 2 * 4)(sp)
61 sw $3, ( 3 * 4)(sp)
62 sw $4, ( 4 * 4)(sp)
63 sw $5, ( 5 * 4)(sp)
64 sw $6, ( 6 * 4)(sp)
65 sw $7, ( 7 * 4)(sp)
[all …]
/nrf52832-nimble/rt-thread/components/net/lwip-2.0.2/src/apps/lwiperf/
H A Dlwiperf.c121 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
122 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
123 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
124 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
125 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
126 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
127 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
128 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
129 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
130 …0','1','2','3','4','5','6','7','8','9','0','1','2','3','4','5','6','7','8','9','0','1','2','3','4'…
[all …]
/nrf52832-nimble/rt-thread/components/net/lwip-2.1.0/src/apps/lwiperf/
H A Dlwiperf.c136 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
137 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
138 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
139 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
140 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
141 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
142 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
143 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
144 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
145 …'4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3'…
[all …]
/nrf52832-nimble/rt-thread/components/dfs/filesystems/uffs/src/uffs/
H A Duffs_ecc.c45 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4,
46 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
47 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
48 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
49 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
50 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
51 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
52 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
53 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
54 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
[all …]
/nrf52832-nimble/rt-thread/libcpu/mips/x1000/
H A Dstartup_gcc.S36 ALIGN(4)
42 ALIGN(4)
80 /* init caches, assumes a 4way * 128set * 32byte I/D cache */
132 .section .vectors.4, "ax", %progbits
167 sw $0, (4*0)(sp);
168 sw $1, (4*1)(sp);
169 sw $2, (4*2)(sp);
170 sw $3, (4*3)(sp);
171 sw $4, (4*4)(sp);
172 sw $5, (4*5)(sp);
[all …]
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/pts/tpg/
H A D94654-20170317-085441153.pts8 <item><table>1</table><row>4</row></item>
25 <item><table>0a</table><row>4</row></item>
41 <item><table>20</table><row>4</row></item>
53 <item><table>20A</table><row>4</row></item>
61 <item><table>21</table><row>4</row></item>
70 <item><table>22</table><row>4</row></item>
74 <item><table>23</table><row>4</row></item>
79 <item><table>24</table><row>4</row></item>
83 <item><table>25</table><row>4</row></item>
90 <item><table>26</table><row>4</row></item>
[all …]
H A D94654-20170317-085122560.tpg4 MA9F,FJO2P^3:4_]04%-0T%9=^XCMWKF"L$[)%)G>_I 0Q?@:H)&1HX)7VY&.
5 M3 *!JH;^YUJ1[_*7JN2'Z5^*0I&NP+[LAE:>S92BP^T:3+B>IKFJJ8A,4Y^L
7 MG>K?^<ZA'-8.RL-J$<)(C9[Q!,J#I\O^U //$%L+CAC;BZR I+VL1_?1UG&4
8 M!5L,T[F[JEFYD;^4JYE2JO%6O=+:CXZ6CL\:\-LP1(%UF9F8$Q"A4XJ_PM#^
9 M^G*CZ8!#KXH7096+O4QZ6O<)Y-4PO:<0N*]7B9PRW"'X3YL(Z^S%XUB5@[F_
17 MGZT#BI_?NH.HFKN/E?B#&*\.!<2?KFV9BD>%4ZV$FK^(F[P B/[TU86=H%S^
18 MH[H^EYQB:MZ)A:2@IV)4O=//SXNP#%F]5N&<3KZL>(#6'H"D4\DST(O!(![@
25 M6C/PV(36QT(9B9^.C)*YUP?BN>#F%4ST/JM>\*Y;K)J:S<F0V:R=A)% E4*K
27 MSO#(?)&QE;>+4[O%?G[S[L"<B<&$DE6: Z&6J=*%J]0=\*/]\+$_F9!R$\4@
30 MAY^ (+Y+V8GD:B</')R,'%225'-E,!4W[\60BHNOAZ$,/R>'!S H%G*;=[-\
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/arm926/
H A Dstart_gcc.S16 #define S_FRAME_SIZE (18*4) //72
18 @#define S_SPSR (17*4) //SPSR
19 @#define S_CPSR (16*4) //CPSR
20 #define S_PC (15*4) //R15
21 @#define S_LR (14*4) //R14
22 @#define S_SP (13*4) //R13
24 @#define S_IP (12*4) //R12
25 @#define S_FP (11*4) //R11
26 @#define S_R10 (10*4)
27 @#define S_R9 (9*4)
[all …]
H A Dstart_iar.S16 #define S_FRAME_SIZE (18*4) ;72
18 ;#define S_SPSR (17*4) ;SPSR
19 ;#define S_CPSR (16*4) ;CPSR
20 #define S_PC (15*4) ;R15
21 ;#define S_LR (14*4) ;R14
22 ;#define S_SP (13*4) ;R13
24 ;#define S_IP (12*4) ;R12
25 ;#define S_FP (11*4) ;R11
26 ;#define S_R10 (10*4)
27 ;#define S_R9 (9*4)
[all …]
/nrf52832-nimble/rt-thread/components/libc/compilers/minilibc/
H A Dmath.c48 * Example with 4 iterations: in sin()
49 * result = 1 - x^2/2! + x^4/4! - x^6/6! + x^8/8! in sin()
52 * result = 1 - x^2 * (1/2! - x^2 * (1/4! - x^2 * (1/6! - x^2 * (1/8!)))) in sin()
59 result += 1./(1.*2*3*4*5*6*7*8*9*10*11*12*13*14*15*16*17*18*19*20); in sin()
63 result += 1./(1.*2*3*4*5*6*7*8*9*10*11*12*13*14*15*16*17*18); in sin()
67 result += 1./(1.*2*3*4*5*6*7*8*9*10*11*12*13*14*15*16); in sin()
71 result += 1./(1.*2*3*4*5*6*7*8*9*10*11*12*13*14); in sin()
75 result += 1./(1.*2*3*4*5*6*7*8*9*10*11*12); in sin()
79 result += 1./(1.*2*3*4*5*6*7*8*9*10); in sin()
82 result += 1./(1.*2*3*4*5*6*7*8); in sin()
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/s3c44b0/
H A Dstart_rvds.S82 ;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM)
86 ;// <o1.4> RSE: Read Stall Enable
90 ;// <i> SA = (Start Address) / 4k
92 ;// <i> SE = (End Address + 1) / 4k
96 ;// <i> SA = (Start Address) / 4k
98 ;// <i> SE = (End Address + 1) / 4k
103 ;// <o4.6..7> LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
104 ;// <o4.4..5> ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
105 ;// <o4.2..3> BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
106 ;// <o4.0..1> nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
[all …]
/nrf52832-nimble/nordic/nrfx/templates/nRF52840/
H A Dnrfx_config.h37 // <4=> 4
57 // <4=> Debug
69 // <4=> Yellow
85 // <4=> Yellow
109 // <4=> VDD
161 // <4=> 4
176 // <4=> 4
196 // <4=> Debug
208 // <4=> Yellow
224 // <4=> Yellow
[all …]
/nrf52832-nimble/rt-thread/components/net/lwip_dhcpd/
H A Ddhcp_server_raw.c379 SMEMCPY(&msg->siaddr, &(dhcp_server->netif->ip_addr), 4); in dhcp_server_recv()
383 SMEMCPY(&msg->yiaddr, &node->ipaddr, 4); in dhcp_server_recv()
393 *opt_buf++ = 4; in dhcp_server_recv()
394 SMEMCPY(opt_buf, &(dhcp_server->netif->ip_addr), 4); in dhcp_server_recv()
395 opt_buf += 4; in dhcp_server_recv()
399 *opt_buf++ = 4; in dhcp_server_recv()
401 SMEMCPY(opt_buf, &tmp, 4); in dhcp_server_recv()
402 opt_buf += 4; in dhcp_server_recv()
406 *opt_buf++ = 4; in dhcp_server_recv()
407 SMEMCPY(opt_buf, &ip_2_ip4(&dhcp_server->netif->netmask)->addr, 4); in dhcp_server_recv()
[all …]
/nrf52832-nimble/nordic/nrfx/templates/nRF52810/
H A Dnrfx_config.h37 // <4=> 4
57 // <4=> Debug
69 // <4=> Yellow
85 // <4=> Yellow
109 // <4=> VDD
161 // <4=> 4
176 // <4=> 4
196 // <4=> Debug
208 // <4=> Yellow
224 // <4=> Yellow
[all …]
/nrf52832-nimble/drivers/
H A Dnrfx_config.h37 // <4=> 4
57 // <4=> Debug
69 // <4=> Yellow
85 // <4=> Yellow
109 // <4=> VDD
161 // <4=> 4
176 // <4=> 4
196 // <4=> Debug
208 // <4=> Yellow
224 // <4=> Yellow
[all …]
/nrf52832-nimble/nordic/nrfx/templates/nRF52832/
H A Dnrfx_config.h37 // <4=> 4
57 // <4=> Debug
69 // <4=> Yellow
85 // <4=> Yellow
109 // <4=> VDD
161 // <4=> 4
176 // <4=> 4
196 // <4=> Debug
208 // <4=> Yellow
224 // <4=> Yellow
[all …]
/nrf52832-nimble/nordic/nrfx/templates/nRF9160/
H A Dnrfx_config.h100 // <4=> 4
120 // <4=> Debug
132 // <4=> Yellow
148 // <4=> Yellow
178 // <4=> Debug
190 // <4=> Yellow
206 // <4=> Yellow
236 // <4=> 4
256 // <4=> Debug
268 // <4=> Yellow
[all …]
/nrf52832-nimble/rt-thread/libcpu/mips/loongson_1c/
H A Dcache_gcc.S42 addiu t7, $0, 4 #4 way
50 addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12)
57 addiu t3, $0, 4 #4 way
65 addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12)
91 beq t7, 1, 4f
93 beq t7, 2 ,4f
95 cache Index_Store_Tag_D, 0x2(v0) # 4 way
97 4: beq $0, $0, 1b
106 beq t3, 1, 4f
108 beq t3, 2, 4f
[all …]
/nrf52832-nimble/rt-thread/libcpu/mips/loongson_1b/
H A Dcache_gcc.S41 addiu t7, $0, 4 #4 way
49 addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12)
56 addiu t3, $0, 4 #4 way
64 addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12)
90 beq t7, 1, 4f
92 beq t7, 2 ,4f
94 cache Index_Store_Tag_D, 0x2(v0) # 4 way
96 4: beq $0, $0, 1b
105 beq t3, 1, 4f
107 beq t3, 2, 4f
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/s3c24x0/
H A Dstart_rvds.S107 ;// <o1.3..4> Clock Division Factor
141 ;// <o2.4..9> p: Pre-divider p Value <3-64><#-2>
150 ;// <o3.4..9> p: Pre-divider p Value <2-65><#-2>
172 ;// <o4.4> NAND FLASH Controller Enable
179 ;// <o5.4> SLOW_BIT: Slow Mode Enable
189 ;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8
200 ;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4
205 ;// <o7.4> CAMCLK Select
231 BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset
254 ;// <o1.19> ST4: Use UB/LB for Bank 4
[all …]
/nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/
H A Dcontext.h9 #define GPR2 4
39 #define USPRG0 (GPR31 + 4)
40 #define CR (USPRG0 + 4)
41 #define XER (CR + 4)
42 #define CTR (XER + 4)
43 #define LR (CTR + 4)
44 #define SRR0 (LR + 4)
45 #define SRR1 (SRR0 + 4)
46 #define STACK_FRAME_SIZE (SRR1 + 4)
/nrf52832-nimble/rt-thread/examples/libc/
H A Dprintf.c96 printf("#%.4x %4x#\n", 4, 88); in printf_test()
97 printf("#%4x#\n",4); in printf_test()
116 printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 16, "KEY_A1", "key_a1"); in printf_test()
117 printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 2, "KEY_A1", "key_a1"); in printf_test()
118 printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 2, 16, "KEY_A1", "key_a1"); in printf_test()
119 printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 16, 0, "KEY_A1", "key_a1"); in printf_test()
120 printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 0, 16, "KEY_A1", "key_a1"); in printf_test()
121 printf("{ %4d, %-*.*s },\t/* %s */\n", 139, 0, 0, "KEY_A1", "key_a1"); in printf_test()
122 printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 16, "KEY_A1", "key_a1"); in printf_test()
123 printf("{ %4d, %*.*s },\t/* %s */\n", 139, 16, 2, "KEY_A1", "key_a1"); in printf_test()
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/zynq7000/
H A Dgic.c36 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + (n/32) * 4)
37 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4)
38 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4)
42 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4)
43 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4)
44 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + (n/16) * 4)
46 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + (n/4) * 4)
99 old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); in arm_gic_set_cpu()
100 old_tgt |= cpumask << ((irq % 4)*8); in arm_gic_set_cpu()
123 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, in arm_gic_dump_type()
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/realview-a8-vmm/
H A Dgic.c37 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
38 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
39 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
40 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
41 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
42 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
43 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4)
44 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4)
45 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4)
46 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
[all …]
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/test/src/
H A Dble_gatt_read_test.c249 ble_hs_test_util_create_conn(2, ((uint8_t[]){2,3,4,5,6,7,8,9}), in ble_gatt_read_test_misc_verify_good()
275 ble_hs_test_util_create_conn(2, ((uint8_t[]){2,3,4,5,6,7,8,9}), in ble_gatt_read_test_misc_verify_bad()
301 ble_hs_test_util_create_conn(2, ((uint8_t[]){2,3,4,5,6,7,8,9}), in ble_gatt_read_test_misc_uuid_verify_good()
348 ble_hs_test_util_create_conn(2, ((uint8_t[]){2,3,4,5,6,7,8,9}), in ble_gatt_read_test_misc_long_verify_good()
397 ble_hs_test_util_create_conn(2, ((uint8_t[]){2,3,4,5,6,7,8,9}), in ble_gatt_read_test_misc_long_verify_bad()
438 ble_hs_test_util_create_conn(2, ((uint8_t[]){2,3,4,5,6,7,8,9}), in ble_gatt_read_test_misc_mult_verify_good()
482 ble_hs_test_util_create_conn(2, ((uint8_t[]){2,3,4,5,6,7,8,9}), in ble_gatt_read_test_misc_mult_verify_bad()
506 .value = { 1,2,3,4,5,6,7 }, in TEST_CASE()
530 .value = { 1,2,3,4,5,6,7 }, in TEST_CASE()
549 .value = { 1,2,3,4,5,6,7 }, in TEST_CASE()
[all …]

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