1 /* 2 * File : mips_context_asm.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2016��9��7�� Urey the first version 23 */ 24 25 #ifndef _MIPS_CONTEXT_ASM_H_ 26 #define _MIPS_CONTEXT_ASM_H_ 27 28 #define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) 29 #ifdef __mips_hard_float 30 #define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ 31 #define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) 32 #else 33 #define FPU_ADJ 0 34 #endif 35 36 37 38 #ifdef __ASSEMBLY__ 39 40 #ifdef __mips_hard_float 41 .global _fpctx_save 42 .global _fpctx_load 43 #endif 44 45 .macro SAVE_CONTEXT 46 .set push 47 .set noat 48 .set noreorder 49 .set volatile 50 51 //save SP 52 move k1, sp 53 move k0, sp 54 subu sp, k1, CONTEXT_SIZE 55 sw k0, (29 * 4)(sp) 56 57 //save REG 58 sw $0, ( 0 * 4)(sp) 59 sw $1, ( 1 * 4)(sp) 60 sw $2, ( 2 * 4)(sp) 61 sw $3, ( 3 * 4)(sp) 62 sw $4, ( 4 * 4)(sp) 63 sw $5, ( 5 * 4)(sp) 64 sw $6, ( 6 * 4)(sp) 65 sw $7, ( 7 * 4)(sp) 66 sw $8, ( 8 * 4)(sp) 67 sw $9, ( 9 * 4)(sp) 68 sw $10, (10 * 4)(sp) 69 sw $11, (11 * 4)(sp) 70 sw $12, (12 * 4)(sp) 71 sw $13, (13 * 4)(sp) 72 sw $14, (14 * 4)(sp) 73 sw $15, (15 * 4)(sp) 74 sw $16, (16 * 4)(sp) 75 sw $17, (17 * 4)(sp) 76 sw $18, (18 * 4)(sp) 77 sw $19, (19 * 4)(sp) 78 sw $20, (20 * 4)(sp) 79 sw $21, (21 * 4)(sp) 80 sw $22, (22 * 4)(sp) 81 sw $23, (23 * 4)(sp) 82 sw $24, (24 * 4)(sp) 83 sw $25, (25 * 4)(sp) 84 /* K0 K1 */ 85 sw $28, (28 * 4)(sp) 86 /* SP */ 87 sw $30, (30 * 4)(sp) 88 sw $31, (31 * 4)(sp) 89 90 /* STATUS CAUSE EPC.... */ 91 mfc0 $2, CP0_STATUS 92 sw $2, STK_OFFSET_SR(sp) 93 94 mfc0 $2, CP0_CAUSE 95 sw $2, STK_OFFSET_CAUSE(sp) 96 97 mfc0 $2, CP0_BADVADDR 98 sw $2, STK_OFFSET_BADVADDR(sp) 99 100 MFC0 $2, CP0_EPC 101 sw $2, STK_OFFSET_EPC(sp) 102 103 mfhi $2 104 sw $2, STK_OFFSET_HI(sp) 105 106 mflo $2 107 sw $2, STK_OFFSET_LO(sp) 108 #ifdef __mips_hard_float 109 add a0, sp,STK_CTX_SIZE 110 111 mfc0 t0, CP0_STATUS 112 .set push 113 .set at 114 or t0, M_StatusCU1 115 .set push 116 mtc0 t0, CP0_STATUS 117 118 cfc1 t0, CP1_STATUS 119 sw t0 , 0x00(a0) 120 swc1 $f0,(0x04 * 1)(a0) 121 swc1 $f1,(0x04 * 2)(a0) 122 swc1 $f2,(0x04 * 3)(a0) 123 swc1 $f3,(0x04 * 4)(a0) 124 swc1 $f4,(0x04 * 5)(a0) 125 swc1 $f5,(0x04 * 6)(a0) 126 swc1 $f6,(0x04 * 7)(a0) 127 swc1 $f7,(0x04 * 8)(a0) 128 swc1 $f8,(0x04 * 9)(a0) 129 swc1 $f9,(0x04 * 10)(a0) 130 swc1 $f10,(0x04 * 11)(a0) 131 swc1 $f11,(0x04 * 12)(a0) 132 swc1 $f12,(0x04 * 13)(a0) 133 swc1 $f13,(0x04 * 14)(a0) 134 swc1 $f14,(0x04 * 15)(a0) 135 swc1 $f15,(0x04 * 16)(a0) 136 swc1 $f16,(0x04 * 17)(a0) 137 swc1 $f17,(0x04 * 18)(a0) 138 swc1 $f18,(0x04 * 19)(a0) 139 swc1 $f19,(0x04 * 20)(a0) 140 swc1 $f20,(0x04 * 21)(a0) 141 swc1 $f21,(0x04 * 22)(a0) 142 swc1 $f22,(0x04 * 23)(a0) 143 swc1 $f23,(0x04 * 24)(a0) 144 swc1 $f24,(0x04 * 25)(a0) 145 swc1 $f25,(0x04 * 26)(a0) 146 swc1 $f26,(0x04 * 27)(a0) 147 swc1 $f27,(0x04 * 28)(a0) 148 swc1 $f28,(0x04 * 29)(a0) 149 swc1 $f29,(0x04 * 30)(a0) 150 swc1 $f30,(0x04 * 31)(a0) 151 swc1 $f31,(0x04 * 32)(a0) 152 153 nop 154 #endif 155 156 //restore a0 157 lw a0, (REG_A0 * 4)(sp) 158 159 .set pop 160 .endm 161 162 163 .macro RESTORE_CONTEXT 164 .set push 165 .set noat 166 .set noreorder 167 .set volatile 168 169 #ifdef __mips_hard_float 170 add a0, sp,STK_CTX_SIZE 171 172 mfc0 t0, CP0_STATUS 173 .set push 174 .set at 175 or t0, M_StatusCU1 176 .set noat 177 mtc0 t0, CP0_STATUS 178 179 lw t0 , 0x00(a0) 180 lwc1 $f0,(0x04 * 1)(a0) 181 lwc1 $f1,(0x04 * 2)(a0) 182 lwc1 $f2,(0x04 * 3)(a0) 183 lwc1 $f3,(0x04 * 4)(a0) 184 lwc1 $f4,(0x04 * 5)(a0) 185 lwc1 $f5,(0x04 * 6)(a0) 186 lwc1 $f6,(0x04 * 7)(a0) 187 lwc1 $f7,(0x04 * 8)(a0) 188 lwc1 $f8,(0x04 * 9)(a0) 189 lwc1 $f9,(0x04 * 10)(a0) 190 lwc1 $f10,(0x04 * 11)(a0) 191 lwc1 $f11,(0x04 * 12)(a0) 192 lwc1 $f12,(0x04 * 13)(a0) 193 lwc1 $f13,(0x04 * 14)(a0) 194 lwc1 $f14,(0x04 * 15)(a0) 195 lwc1 $f15,(0x04 * 16)(a0) 196 lwc1 $f16,(0x04 * 17)(a0) 197 lwc1 $f17,(0x04 * 18)(a0) 198 lwc1 $f18,(0x04 * 19)(a0) 199 lwc1 $f19,(0x04 * 20)(a0) 200 lwc1 $f20,(0x04 * 21)(a0) 201 lwc1 $f21,(0x04 * 22)(a0) 202 lwc1 $f22,(0x04 * 23)(a0) 203 lwc1 $f23,(0x04 * 24)(a0) 204 lwc1 $f24,(0x04 * 25)(a0) 205 lwc1 $f25,(0x04 * 26)(a0) 206 lwc1 $f26,(0x04 * 27)(a0) 207 lwc1 $f27,(0x04 * 28)(a0) 208 lwc1 $f28,(0x04 * 29)(a0) 209 lwc1 $f29,(0x04 * 30)(a0) 210 lwc1 $f30,(0x04 * 31)(a0) 211 lwc1 $f31,(0x04 * 32)(a0) 212 ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ 213 214 nop 215 #endif 216 217 /* ͨ�üĴ��� */ 218 /* ZERO */ 219 lw $1, ( 1 * 4)(sp) 220 /* V0 */ 221 lw $3, ( 3 * 4)(sp) 222 lw $4, ( 4 * 4)(sp) 223 lw $5, ( 5 * 4)(sp) 224 lw $6, ( 6 * 4)(sp) 225 lw $7, ( 7 * 4)(sp) 226 lw $8, ( 8 * 4)(sp) 227 lw $9, ( 9 * 4)(sp) 228 lw $10, (10 * 4)(sp) 229 lw $11, (11 * 4)(sp) 230 lw $12, (12 * 4)(sp) 231 lw $13, (13 * 4)(sp) 232 lw $14, (14 * 4)(sp) 233 lw $15, (15 * 4)(sp) 234 lw $16, (16 * 4)(sp) 235 lw $17, (17 * 4)(sp) 236 lw $18, (18 * 4)(sp) 237 lw $19, (19 * 4)(sp) 238 lw $20, (20 * 4)(sp) 239 lw $21, (21 * 4)(sp) 240 lw $22, (22 * 4)(sp) 241 lw $23, (23 * 4)(sp) 242 lw $24, (24 * 4)(sp) 243 lw $25, (25 * 4)(sp) 244 lw $26, (26 * 4)(sp) 245 lw $27, (27 * 4)(sp) 246 lw $28, (28 * 4)(sp) 247 /* SP */ 248 lw $30, (30 * 4)(sp) 249 lw $31, (31 * 4)(sp) 250 251 252 /* STATUS CAUSE EPC.... */ 253 lw $2, STK_OFFSET_HI(sp) 254 mthi $2 255 lw $2, STK_OFFSET_LO(sp) 256 mtlo $2 257 258 lw $2, STK_OFFSET_SR(sp) 259 mtc0 $2, CP0_STATUS 260 261 lw $2, STK_OFFSET_BADVADDR(sp) 262 mtc0 $2, CP0_BADVADDR 263 264 lw $2, STK_OFFSET_CAUSE(sp) 265 mtc0 $2, CP0_CAUSE 266 267 lw $2, STK_OFFSET_EPC(sp) 268 MTC0 $2, CP0_EPC 269 270 //restore $2 271 lw $2, ( 2 * 4)(sp) 272 //restore sp 273 lw $29, (29 * 4)(sp) 274 275 eret 276 nop 277 .set pop 278 .endm 279 #endif 280 #endif /* _MIPS_CONTEXT_ASM_H_ */ 281