1/* 2 * File : cache_gcc.S 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team 5 * 6 * The license and distribution terms for this file may be 7 * found in the file LICENSE in this distribution or at 8 * http://www.rt-thread.org/license/LICENSE 9 * 10 * Change Logs: 11 * Date Author Notes 12 * 2010-05-17 swkyer first version 13 * 2010-09-11 bernard port to Loongson SoC3210 14 * 2011-08-08 lgnq port to Loongson LS1B 15 * 2015-07-08 chinesebear port to Loongson LS1C 16 */ 17#include "../common/mipsregs.h" 18#include "../common/mips.inc" 19#include "../common/asm.h" 20#include "cache.h" 21 22 .ent cache_init 23 .global cache_init 24 .set noreorder 25cache_init: 26 move t1,ra 27####part 2#### 28cache_detect_4way: 29 mfc0 t4, CP0_CONFIG 30 andi t5, t4, 0x0e00 31 srl t5, t5, 9 #ic 32 andi t6, t4, 0x01c0 33 srl t6, t6, 6 #dc 34 addiu t8, $0, 1 35 addiu t9, $0, 2 36 #set dcache way 37 beq t6, $0, cache_d1way 38 addiu t7, $0, 1 #1 way 39 beq t6, t8, cache_d2way 40 addiu t7, $0, 2 #2 way 41 beq $0, $0, cache_d4way 42 addiu t7, $0, 4 #4 way 43cache_d1way: 44 beq $0, $0, 1f 45 addiu t6, t6, 12 #1 way 46cache_d2way: 47 beq $0, $0, 1f 48 addiu t6, t6, 11 #2 way 49cache_d4way: 50 addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12) 511: #set icache way 52 beq t5, $0, cache_i1way 53 addiu t3, $0, 1 #1 way 54 beq t5, t8, cache_i2way 55 addiu t3, $0, 2 #2 way 56 beq $0, $0, cache_i4way 57 addiu t3, $0, 4 #4 way 58cache_i1way: 59 beq $0, $0, 1f 60 addiu t5, t5, 12 61cache_i2way: 62 beq $0, $0, 1f 63 addiu t5, t5, 11 64cache_i4way: 65 addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12) 66 671: addiu t4, $0, 1 68 sllv t6, t4, t6 69 sllv t5, t4, t5 70#if 0 71 la t0, memvar 72 sw t7, 0x0(t0) #ways 73 sw t5, 0x4(t0) #icache size 74 sw t6, 0x8(t0) #dcache size 75#endif 76####part 3#### 77 .set mips3 78 lui a0, 0x8000 79 addu a1, $0, t5 80 addu a2, $0, t6 81cache_init_d2way: 82#a0=0x80000000, a1=icache_size, a2=dcache_size 83#a3, v0 and v1 used as local registers 84 mtc0 $0, CP0_TAGHI 85 addu v0, $0, a0 86 addu v1, a0, a2 871: slt a3, v0, v1 88 beq a3, $0, 1f 89 nop 90 mtc0 $0, CP0_TAGLO 91 beq t7, 1, 4f 92 cache Index_Store_Tag_D, 0x0(v0) # 1 way 93 beq t7, 2 ,4f 94 cache Index_Store_Tag_D, 0x1(v0) # 2 way 95 cache Index_Store_Tag_D, 0x2(v0) # 4 way 96 cache Index_Store_Tag_D, 0x3(v0) 974: beq $0, $0, 1b 98 addiu v0, v0, 0x20 991: 100cache_flush_i2way: 101 addu v0, $0, a0 102 addu v1, a0, a1 1031: slt a3, v0, v1 104 beq a3, $0, 1f 105 nop 106 beq t3, 1, 4f 107 cache Index_Invalidate_I, 0x0(v0) # 1 way 108 beq t3, 2, 4f 109 cache Index_Invalidate_I, 0x1(v0) # 2 way 110 cache Index_Invalidate_I, 0x2(v0) 111 cache Index_Invalidate_I, 0x3(v0) # 4 way 1124: beq $0, $0, 1b 113 addiu v0, v0, 0x20 1141: 115cache_flush_d2way: 116 addu v0, $0, a0 117 addu v1, a0, a2 1181: slt a3, v0, v1 119 beq a3, $0, 1f 120 nop 121 beq t7, 1, 4f 122 cache Index_Writeback_Inv_D, 0x0(v0) #1 way 123 beq t7, 2, 4f 124 cache Index_Writeback_Inv_D, 0x1(v0) # 2 way 125 cache Index_Writeback_Inv_D, 0x2(v0) 126 cache Index_Writeback_Inv_D, 0x3(v0) # 4 way 1274: beq $0, $0, 1b 128 addiu v0, v0, 0x20 1291: 130cache_init_finish: 131 jr t1 132 nop 133 .set reorder 134 .end cache_init 135 136########################### 137# Enable CPU cache # 138########################### 139 140LEAF(enable_cpu_cache) 141 .set noreorder 142 mfc0 t0, CP0_CONFIG 143 nop 144 and t0, ~0x03 145 or t0, 0x03 146 mtc0 t0, CP0_CONFIG 147 nop 148 .set reorder 149 j ra 150END (enable_cpu_cache) 151 152########################### 153# disable CPU cache # 154########################### 155 156LEAF(disable_cpu_cache) 157 .set noreorder 158 mfc0 t0, CP0_CONFIG 159 nop 160 and t0, ~0x03 161 or t0, 0x2 162 mtc0 t0, CP0_CONFIG 163 nop 164 .set reorder 165 j ra 166END (disable_cpu_cache) 167 168/**********************************/ 169/* Invalidate Instruction Cache */ 170/**********************************/ 171LEAF(Clear_TagLo) 172 .set noreorder 173 mtc0 zero, CP0_TAGLO 174 nop 175 .set reorder 176 j ra 177END(Clear_TagLo) 178 179 .set mips3 180/**********************************/ 181/* Invalidate Instruction Cache */ 182/**********************************/ 183LEAF(Invalidate_Icache_Ls1c) 184 .set noreorder 185 cache Index_Invalidate_I,0(a0) 186 cache Index_Invalidate_I,1(a0) 187 cache Index_Invalidate_I,2(a0) 188 cache Index_Invalidate_I,3(a0) 189 .set reorder 190 j ra 191END(Invalidate_Icache_Ls1c) 192 193/**********************************/ 194/* Invalidate Data Cache */ 195/**********************************/ 196LEAF(Invalidate_Dcache_ClearTag_Ls1c) 197 .set noreorder 198 cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag 199 cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag 200 .set reorder 201 j ra 202END(Invalidate_Dcache_ClearTag_Ls1c) 203 204LEAF(Invalidate_Dcache_Fill_Ls1c) 205 .set noreorder 206 cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag 207 cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag 208 .set reorder 209 j ra 210END(Invalidate_Dcache_Fill_Ls1c) 211 212LEAF(Writeback_Invalidate_Dcache) 213 .set noreorder 214 cache Hit_Writeback_Inv_D, (a0) 215 .set reorder 216 j ra 217END(Writeback_Invalidate_Dcache) 218 .set mips0 219