Lines Matching full:4
107 ;// <o1.3..4> Clock Division Factor
141 ;// <o2.4..9> p: Pre-divider p Value <3-64><#-2>
150 ;// <o3.4..9> p: Pre-divider p Value <2-65><#-2>
172 ;// <o4.4> NAND FLASH Controller Enable
179 ;// <o5.4> SLOW_BIT: Slow Mode Enable
189 ;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8
200 ;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4
205 ;// <o7.4> CAMCLK Select
231 BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset
254 ;// <o1.19> ST4: Use UB/LB for Bank 4
255 ;// <o1.18> WS4: Enable Wait Status for Bank 4
256 ;// <o1.16..17> DW4: Data Bus Width for Bank 4
268 ;// <o1.4..5> DW1: Data Bus Width for Bank 1
275 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
277 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
279 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
280 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
282 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
283 ;// <o2.4..5> Tcah: Address Hold Time after nGCS
284 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
286 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
288 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
292 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
294 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
296 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
297 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
299 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
300 ;// <o3.4..5> Tcah: Address Hold Time after nGCS
301 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
303 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
305 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
309 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
311 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
313 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
314 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
316 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
317 ;// <o4.4..5> Tcah: Address Hold Time after nGCS
318 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
320 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
322 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
326 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
328 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
330 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
331 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
333 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
334 ;// <o5.4..5> Tcah: Address Hold Time after nGCS
335 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
337 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
339 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
341 ;// <h> Bank 4 Control Register (BANKCON4)
343 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
345 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
347 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
348 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
350 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
351 ;// <o6.4..5> Tcah: Address Hold Time after nGCS
352 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
354 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
356 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
360 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
362 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
364 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
365 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
367 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
368 ;// <o7.4..5> Tcah: Address Hold Time after nGCS
369 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
371 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
373 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
379 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
381 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
383 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
384 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
386 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
387 ;// <o8.4..5> Tcah: Address Hold Time after nGCS
388 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
393 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
402 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
404 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
406 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
407 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
409 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
410 ;// <o9.4..5> Tcah: Address Hold Time after nGCS
411 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
416 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
426 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved
429 ;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
436 ;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle
440 ;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB
449 ;// <o12.4..6> CL: CAS Latency
461 ;// <o13.4..6> CL: CAS Latency
512 ;// <o1.15> GPA15 <0=> Output <1=> nGCS[4]
523 ;// <o1.4> GPA4 <0=> Output <1=> ADDR19
543 ;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved
554 ;// <o2.4> GPB4 Pull-up Disable
570 ;// <o1.24..25> GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved
580 ;// <o1.4..5> GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
596 ;// <o2.4> GPC4 Pull-up Disable
622 ;// <o1.4..5> GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved
638 ;// <o2.4> GPD4 Pull-up Disable
666 ;// <o1.4..5> GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET
680 ;// <o2.4> GPE4 Pull-up Disable
696 ;// <o1.8..9> GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved
698 ;// <o1.4..5> GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved
706 ;// <o2.4> GPF4 Pull-up Disable
732 ;// <o1.4..5> GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0
748 ;// <o2.4> GPG4 Pull-up Disable
769 ;// <o1.4..5> GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved
780 ;// <o2.4> GPH4 Pull-up Disable
801 ;// <o1.8..9> GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved
803 ;// <o1.4..5> GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved
816 ;// <o2.4> GPJ4 Pull-up Disable
889 str r6, [r8, #4] ;/* Save CPSR */
1120 SUBS pc, lr, #4
1135 SUB r2, lr, #4 ; save old task's pc to r2