1/* 2 * File : cache_gcc.S 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team 5 * 6 * The license and distribution terms for this file may be 7 * found in the file LICENSE in this distribution or at 8 * http://www.rt-thread.org/license/LICENSE 9 * 10 * Change Logs: 11 * Date Author Notes 12 * 2010-05-17 swkyer first version 13 * 2010-09-11 bernard port to Loongson SoC3210 14 * 2011-08-08 lgnq port to Loongson LS1B 15 */ 16#include "../common/mipsregs.h" 17#include "../common/mips.inc" 18#include "../common/asm.h" 19#include "cache.h" 20 21 .ent cache_init 22 .global cache_init 23 .set noreorder 24cache_init: 25 move t1,ra 26####part 2#### 27cache_detect_4way: 28 mfc0 t4, CP0_CONFIG 29 andi t5, t4, 0x0e00 30 srl t5, t5, 9 #ic 31 andi t6, t4, 0x01c0 32 srl t6, t6, 6 #dc 33 addiu t8, $0, 1 34 addiu t9, $0, 2 35 #set dcache way 36 beq t6, $0, cache_d1way 37 addiu t7, $0, 1 #1 way 38 beq t6, t8, cache_d2way 39 addiu t7, $0, 2 #2 way 40 beq $0, $0, cache_d4way 41 addiu t7, $0, 4 #4 way 42cache_d1way: 43 beq $0, $0, 1f 44 addiu t6, t6, 12 #1 way 45cache_d2way: 46 beq $0, $0, 1f 47 addiu t6, t6, 11 #2 way 48cache_d4way: 49 addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12) 501: #set icache way 51 beq t5, $0, cache_i1way 52 addiu t3, $0, 1 #1 way 53 beq t5, t8, cache_i2way 54 addiu t3, $0, 2 #2 way 55 beq $0, $0, cache_i4way 56 addiu t3, $0, 4 #4 way 57cache_i1way: 58 beq $0, $0, 1f 59 addiu t5, t5, 12 60cache_i2way: 61 beq $0, $0, 1f 62 addiu t5, t5, 11 63cache_i4way: 64 addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12) 65 661: addiu t4, $0, 1 67 sllv t6, t4, t6 68 sllv t5, t4, t5 69#if 0 70 la t0, memvar 71 sw t7, 0x0(t0) #ways 72 sw t5, 0x4(t0) #icache size 73 sw t6, 0x8(t0) #dcache size 74#endif 75####part 3#### 76 .set mips3 77 lui a0, 0x8000 78 addu a1, $0, t5 79 addu a2, $0, t6 80cache_init_d2way: 81#a0=0x80000000, a1=icache_size, a2=dcache_size 82#a3, v0 and v1 used as local registers 83 mtc0 $0, CP0_TAGHI 84 addu v0, $0, a0 85 addu v1, a0, a2 861: slt a3, v0, v1 87 beq a3, $0, 1f 88 nop 89 mtc0 $0, CP0_TAGLO 90 beq t7, 1, 4f 91 cache Index_Store_Tag_D, 0x0(v0) # 1 way 92 beq t7, 2 ,4f 93 cache Index_Store_Tag_D, 0x1(v0) # 2 way 94 cache Index_Store_Tag_D, 0x2(v0) # 4 way 95 cache Index_Store_Tag_D, 0x3(v0) 964: beq $0, $0, 1b 97 addiu v0, v0, 0x20 981: 99cache_flush_i2way: 100 addu v0, $0, a0 101 addu v1, a0, a1 1021: slt a3, v0, v1 103 beq a3, $0, 1f 104 nop 105 beq t3, 1, 4f 106 cache Index_Invalidate_I, 0x0(v0) # 1 way 107 beq t3, 2, 4f 108 cache Index_Invalidate_I, 0x1(v0) # 2 way 109 cache Index_Invalidate_I, 0x2(v0) 110 cache Index_Invalidate_I, 0x3(v0) # 4 way 1114: beq $0, $0, 1b 112 addiu v0, v0, 0x20 1131: 114cache_flush_d2way: 115 addu v0, $0, a0 116 addu v1, a0, a2 1171: slt a3, v0, v1 118 beq a3, $0, 1f 119 nop 120 beq t7, 1, 4f 121 cache Index_Writeback_Inv_D, 0x0(v0) #1 way 122 beq t7, 2, 4f 123 cache Index_Writeback_Inv_D, 0x1(v0) # 2 way 124 cache Index_Writeback_Inv_D, 0x2(v0) 125 cache Index_Writeback_Inv_D, 0x3(v0) # 4 way 1264: beq $0, $0, 1b 127 addiu v0, v0, 0x20 1281: 129cache_init_finish: 130 jr t1 131 nop 132 .set reorder 133 .end cache_init 134 135########################### 136# Enable CPU cache # 137########################### 138 139LEAF(enable_cpu_cache) 140 .set noreorder 141 mfc0 t0, CP0_CONFIG 142 nop 143 and t0, ~0x03 144 or t0, 0x03 145 mtc0 t0, CP0_CONFIG 146 nop 147 .set reorder 148 j ra 149END (enable_cpu_cache) 150 151########################### 152# disable CPU cache # 153########################### 154 155LEAF(disable_cpu_cache) 156 .set noreorder 157 mfc0 t0, CP0_CONFIG 158 nop 159 and t0, ~0x03 160 or t0, 0x2 161 mtc0 t0, CP0_CONFIG 162 nop 163 .set reorder 164 j ra 165END (disable_cpu_cache) 166 167/**********************************/ 168/* Invalidate Instruction Cache */ 169/**********************************/ 170LEAF(Clear_TagLo) 171 .set noreorder 172 mtc0 zero, CP0_TAGLO 173 nop 174 .set reorder 175 j ra 176END(Clear_TagLo) 177 178 .set mips3 179/**********************************/ 180/* Invalidate Instruction Cache */ 181/**********************************/ 182LEAF(Invalidate_Icache_Ls1b) 183 .set noreorder 184 cache Index_Invalidate_I,0(a0) 185 cache Index_Invalidate_I,1(a0) 186 cache Index_Invalidate_I,2(a0) 187 cache Index_Invalidate_I,3(a0) 188 .set reorder 189 j ra 190END(Invalidate_Icache_Ls1b) 191 192/**********************************/ 193/* Invalidate Data Cache */ 194/**********************************/ 195LEAF(Invalidate_Dcache_ClearTag_Ls1b) 196 .set noreorder 197 cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag 198 cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag 199 .set reorder 200 j ra 201END(Invalidate_Dcache_ClearTag_Ls1b) 202 203LEAF(Invalidate_Dcache_Fill_Ls1b) 204 .set noreorder 205 cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag 206 cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag 207 .set reorder 208 j ra 209END(Invalidate_Dcache_Fill_Ls1b) 210 211LEAF(Writeback_Invalidate_Dcache) 212 .set noreorder 213 cache Hit_Writeback_Inv_D, (a0) 214 .set reorder 215 j ra 216END(Writeback_Invalidate_Dcache) 217 .set mips0 218