History log of /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (Results 301 – 325 of 358)
Revision Date Author Comments
# bf9968b2 19-Jul-2020 Yinan Xu <[email protected]>

csr,roq: support interrupt to difftest


# db1d07e1 14-Jul-2020 LinJiawei <[email protected]>

Merge remote-tracking branch 'origin/master' into csr


# b528ac53 14-Jul-2020 LinJiawei <[email protected]>

Block csr inst in roq


# 67aa35f4 14-Jul-2020 LinJiawei <[email protected]>

Log: turn off log at chisel level when we don't need it


# 228ca5bd 14-Jul-2020 LinJiawei <[email protected]>

JmpExeUnit: pass XSConfig to CSR


# fe0fe085 12-Jul-2020 LinJiawei <[email protected]>

Merge master into csr


# 0b2a9073 12-Jul-2020 LinJiawei <[email protected]>

Backend: Block Special Inst in Dispatch Stage


# bcbb079b 12-Jul-2020 ZhangZifei <[email protected]>

Merge branch 'master' into refactor-exu


# a1c4d65b 12-Jul-2020 Yinan Xu <[email protected]>

dispatch2: allow configurations via exuConfig


# 0b791572 11-Jul-2020 ZhangZifei <[email protected]>

Merge branch 'master' into refactor-exu


# 6d95fae2 11-Jul-2020 ZhangZifei <[email protected]>

IssueQueue: all IQ recv bypass and only alu send bypass


# c7cacdf5 11-Jul-2020 Yinan Xu <[email protected]>

Merge remote-tracking branch 'origin/refactor-exu' into improve-dp2


# 65c62b20 11-Jul-2020 LinJiawei <[email protected]>

Merge master into refactor-exu


# cafb3558 11-Jul-2020 LinJiawei <[email protected]>

Refactor exu


# 8557b6ec 11-Jul-2020 Yinan Xu <[email protected]>

dispatch,iq: add numExists to give RS priority


# a25b1bce 07-Jul-2020 LinJiawei <[email protected]>

Bundle/RedirectInfo: use redirectinfo update bpu


# fe16277a 04-Jul-2020 Yinan Xu <[email protected]>

Merge remote-tracking branch 'origin/branch-age' into add-mul-div


# 4ff2b55d 04-Jul-2020 LinJiawei <[email protected]>

Backend: fix diff-test bug


# bc41f016 04-Jul-2020 Yinan Xu <[email protected]>

Merge remote-tracking branch 'origin/branch-age' into add-mul-div


# f4553cb7 04-Jul-2020 Yinan Xu <[email protected]>

lsu: fix forward


# 80d24142 04-Jul-2020 LinJiawei <[email protected]>

Difftest: use arch rat read regfile


# bfa4b2b4 04-Jul-2020 LinJiawei <[email protected]>

Cmp brTag


# e22ba35f 01-Jul-2020 LinJiawei <[email protected]>

fix write back logic


# f9d01431 30-Jun-2020 William Wang <[email protected]>

pipeline: fixing bugs in "dummy" test


# 97cfa7f8 30-Jun-2020 LinJiawei <[email protected]>

Brq: connect to roq


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