1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ 9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 10import xiangshan.backend.rename.Rename 11import xiangshan.backend.brq.Brq 12import xiangshan.backend.dispatch.Dispatch 13import xiangshan.backend.exu._ 14import xiangshan.backend.fu.FunctionUnit 15import xiangshan.backend.issue.IssueQueue 16import xiangshan.backend.regfile.{Regfile, RfWritePort} 17import xiangshan.backend.roq.Roq 18 19 20/** Backend Pipeline: 21 * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe 22 */ 23class Backend(implicit val p: XSConfig) extends XSModule 24 with HasExeUnits 25 with NeedImpl { 26 val io = IO(new Bundle { 27 val dmem = new SimpleBusUC(addrBits = VAddrBits) 28 val memMMU = Flipped(new MemMMUIO) 29 val frontend = Flipped(new FrontendToBackendIO) 30 }) 31 32 33 val decode = Module(new DecodeStage) 34 val brq = Module(new Brq) 35 val decBuf = Module(new DecodeBuffer) 36 val rename = Module(new Rename) 37 val dispatch = Module(new Dispatch(exeUnits.map(_.config))) 38 val roq = Module(new Roq) 39 val intRf = Module(new Regfile( 40 numReadPorts = NRReadPorts, 41 numWirtePorts = NRWritePorts, 42 hasZero = true 43 )) 44 val fpRf = Module(new Regfile( 45 numReadPorts = NRReadPorts, 46 numWirtePorts = NRWritePorts, 47 hasZero = false 48 )) 49 50 // backend redirect, flush pipeline 51 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect) 52 53 val redirectInfo = Wire(new RedirectInfo) 54 // exception or misprediction 55 redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid 56 redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid 57 redirectInfo.redirect := redirect.bits 58 59 var iqInfo = new StringBuilder 60 val issueQueues = exeUnits.zipWithIndex.map({ case (eu, i) => 61 def needBypass(cfg: ExuConfig): Boolean = cfg.enableBypass 62 63 val bypassCnt = exeUnits.map(_.config).count(needBypass) 64 def needWakeup(cfg: ExuConfig): Boolean = 65 (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf) 66 67 val wakeupCnt = exeUnits.map(_.config).count(needWakeup) 68 assert(!(needBypass(eu.config) && !needWakeup(eu.config))) // needBypass but dont needWakeup is not allowed 69 val iq = Module(new IssueQueue( 70 eu.config, 71 wakeupCnt, 72 bypassCnt, 73 eu.config.enableBypass, 74 fifo = eu.config.supportedFuncUnits.contains(FunctionUnit.lsuCfg) 75 )) 76 iq.io.redirect <> redirect 77 iq.io.numExist <> dispatch.io.numExist(i) 78 iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i) 79 iq.io.enqData <> dispatch.io.enqIQData(i) 80 for( 81 (wakeUpPort, exuOut) <- 82 iq.io.wakeUpPorts.zip(exeUnits.filter(e => needWakeup(e.config)).map(_.io.out)) 83 ){ 84 wakeUpPort.bits := exuOut.bits 85 wakeUpPort.valid := exuOut.valid 86 } 87 iqInfo ++= { 88 s"[$i] ${eu.name} Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt" + 89 s" Supported Function:[" + 90 s"${ 91 eu.config.supportedFuncUnits.map( 92 fu => FuType.functionNameMap(fu.fuType.litValue())).mkString(", " 93 ) 94 }]\n" 95 } 96 eu.io.in <> iq.io.deq 97 eu.io.redirect <> redirect 98 iq 99 }) 100 101 val bypassQueues = issueQueues.filter(_.enableBypass) 102 val bypassUnits = exeUnits.filter(_.config.enableBypass) 103 issueQueues.foreach(iq => { 104 for (i <- iq.io.bypassUops.indices) { 105 iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits 106 iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid 107 } 108 iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop) 109 }) 110 111 lsuExeUnits.foreach(_.io.dmem <> io.dmem) 112 lsuExeUnits.foreach(_.io.scommit <> roq.io.scommit) 113 114 io.frontend.redirectInfo <> redirectInfo 115 io.frontend.commits <> roq.io.commits 116 117 decode.io.in <> io.frontend.cfVec 118 brq.io.roqRedirect <> roq.io.redirect 119 brq.io.enqReqs <> decode.io.toBrq 120 for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) { 121 x.bits := y.io.out.bits 122 x.valid := y.io.out.fire() && y.io.out.bits.redirectValid 123 } 124 decode.io.brTags <> brq.io.brTags 125 decBuf.io.redirect <> redirect 126 decBuf.io.in <> decode.io.out 127 128 rename.io.redirect <> redirect 129 rename.io.roqCommits <> roq.io.commits 130 rename.io.in <> decBuf.io.out 131 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 132 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 133 rename.io.intPregRdy <> dispatch.io.intPregRdy 134 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 135 136 dispatch.io.redirect <> redirect 137 dispatch.io.fromRename <> rename.io.out 138 139 roq.io.brqRedirect <> brq.io.redirect 140 roq.io.dp1Req <> dispatch.io.toRoq 141 dispatch.io.roqIdxs <> roq.io.roqIdxs 142 143 intRf.io.readPorts <> dispatch.io.readIntRf 144 fpRf.io.readPorts <> dispatch.io.readFpRf 145 146 val exeWbReqs = exeUnits.map(_.io.out) 147 148 val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.config.writeIntRf).map(_._2) 149 val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.config.writeFpRf).map(_._2) 150 151 val wbu = Module(new Wbu(wbIntIdx, wbFpIdx)) 152 wbu.io.in <> exeWbReqs 153 154 val wbIntResults = wbu.io.toIntRf 155 val wbFpResults = wbu.io.toFpRf 156 157 def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = { 158 val rfWrite = Wire(new RfWritePort) 159 rfWrite.wen := x.valid 160 rfWrite.addr := x.bits.uop.pdest 161 rfWrite.data := x.bits.data 162 rfWrite 163 } 164 165 intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite) 166 fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite) 167 168 rename.io.wbIntResults <> wbIntResults 169 rename.io.wbFpResults <> wbFpResults 170 171 roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2) 172 roq.io.exeWbResults.last := brq.io.out 173 174 175 // TODO: Remove sink and source 176 val tmp = WireInit(0.U) 177 val sinks = Array[String]( 178 "DTLBFINISH", 179 "DTLBPF", 180 "DTLBENABLE", 181 "perfCntCondMdcacheLoss", 182 "perfCntCondMl2cacheLoss", 183 "perfCntCondMdcacheHit", 184 "lsuMMIO", 185 "perfCntCondMl2cacheHit", 186 "perfCntCondMl2cacheReq", 187 "mtip", 188 "perfCntCondMdcacheReq", 189 "meip" 190 ) 191 for (s <- sinks) { 192 BoringUtils.addSink(tmp, s) 193 } 194 195 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 196 BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG") 197 BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG") 198 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 199 if (!p.FPGAPlatform) { 200 BoringUtils.addSource(debugArchReg, "difftestRegs") 201 } 202 203 print(iqInfo) 204 205} 206