xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision a25b1bce7fa49790e996c36694a4737125cc9014) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.issue.IssueQueue
15import xiangshan.backend.regfile.{Regfile, RfWritePort}
16import xiangshan.backend.roq.Roq
17
18
19/** Backend Pipeline:
20  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
21  */
22class Backend(implicit val p: XSConfig) extends XSModule
23  with HasExeUnits
24  with NeedImpl
25{
26  val io = IO(new Bundle {
27    val dmem = new SimpleBusUC(addrBits = VAddrBits)
28    val memMMU = Flipped(new MemMMUIO)
29    val frontend = Flipped(new FrontendToBackendIO)
30  })
31
32
33  val decode = Module(new DecodeStage)
34  val brq = Module(new Brq)
35  val decBuf = Module(new DecodeBuffer)
36  val rename = Module(new Rename)
37  val dispatch = Module(new Dispatch)
38  val roq = Module(new Roq)
39  val intRf = Module(new Regfile(
40    numReadPorts = NRReadPorts,
41    numWirtePorts = NRWritePorts,
42    hasZero = true
43  ))
44  val fpRf = Module(new Regfile(
45    numReadPorts = NRReadPorts,
46    numWirtePorts = NRWritePorts,
47    hasZero = false
48  ))
49
50  // backend redirect, flush pipeline
51  val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect)
52
53  val redirectInfo = Wire(new RedirectInfo)
54  // exception or misprediction
55  redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid
56  redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid
57  redirectInfo.redirect := redirect.bits
58
59  val issueQueues = exeUnits.zipWithIndex.map({ case(eu, i) =>
60    def needBypass(x: Exu): Boolean = eu.enableBypass
61    val bypassCnt = exeUnits.count(needBypass)//if(eu.fuTypeInt == FuType.alu.litValue()) exuConfig.AluCnt else 0
62    def needWakeup(x: Exu): Boolean = (eu.readIntRf && x.writeIntRf) || (eu.readFpRf && x.writeFpRf)
63    val wakeupCnt = exeUnits.count(needWakeup)
64    assert(!(needBypass(eu) && !needWakeup(eu))) // needBypass but dont needWakeup is not allowed
65    val iq = Module(new IssueQueue(eu.fuTypeInt, wakeupCnt, bypassCnt, eu.fixedDelay, fifo = eu.fuTypeInt == FuType.ldu.litValue()))
66    iq.io.redirect <> redirect
67    iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
68    iq.io.enqData <> dispatch.io.enqIQData(i)
69    val wuUnitsOut = exeUnits.filter(e => needWakeup(e)).map(_.io.out)
70    for(i <- iq.io.wakeUpPorts.indices) {
71      iq.io.wakeUpPorts(i).bits <> wuUnitsOut(i).bits
72      iq.io.wakeUpPorts(i).valid := wuUnitsOut(i).valid
73    }
74    println(s"[$i] $eu Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt")
75    eu.io.in <> iq.io.deq
76    eu.io.redirect <> redirect
77    iq
78  })
79
80  val bypassQueues = issueQueues.filter(_.bypassCnt > 0)
81  val bypassUnits = exeUnits.filter(_.enableBypass)
82  bypassQueues.foreach(iq => {
83    for(i <- iq.io.bypassUops.indices) {
84      iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits
85      iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid
86    }
87    iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop)
88  })
89  // val aluQueues = issueQueues.filter(_.fuTypeInt == FuType.alu.litValue())
90  // aluQueues.foreach(aluQ => {
91  //   aluQ.io.bypassUops <> aluQueues.map(_.io.selectedUop)
92  //   aluQ.io.bypassData <> aluExeUnits.map(_.io.out)
93  // })
94
95  lsuExeUnits.foreach(_.io.dmem <> io.dmem)
96  lsuExeUnits.foreach(_.io.scommit <> roq.io.scommit)
97
98  io.frontend.redirectInfo <> redirectInfo
99  io.frontend.commits <> roq.io.commits
100
101  decode.io.in <> io.frontend.cfVec
102  brq.io.roqRedirect <> roq.io.redirect
103  brq.io.enqReqs <> decode.io.toBrq
104  for((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.hasRedirect))){
105    x.bits := y.io.out.bits
106    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
107  }
108  decode.io.brTags <> brq.io.brTags
109  decBuf.io.redirect <> redirect
110  decBuf.io.in <> decode.io.out
111
112  rename.io.redirect <> redirect
113  rename.io.roqCommits <> roq.io.commits
114  rename.io.in <> decBuf.io.out
115  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr)
116  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr)
117  rename.io.intPregRdy <> dispatch.io.intPregRdy
118  rename.io.fpPregRdy <> dispatch.io.fpPregRdy
119
120  dispatch.io.redirect <> redirect
121  dispatch.io.fromRename <> rename.io.out
122
123  roq.io.brqRedirect <> brq.io.redirect
124  roq.io.dp1Req <> dispatch.io.toRoq
125  dispatch.io.roqIdxs <> roq.io.roqIdxs
126
127  intRf.io.readPorts <> dispatch.io.readIntRf
128  fpRf.io.readPorts <> dispatch.io.readFpRf
129
130  val exeWbReqs = exeUnits.map(_.io.out)
131
132  val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.writeIntRf).map(_._2)
133  val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.writeFpRf).map(_._2)
134
135  val wbu = Module(new Wbu(wbIntIdx, wbFpIdx))
136  wbu.io.in <> exeWbReqs
137
138  val wbIntResults = wbu.io.toIntRf
139  val wbFpResults = wbu.io.toFpRf
140
141  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
142    val rfWrite = Wire(new RfWritePort)
143    rfWrite.wen := x.valid
144    rfWrite.addr := x.bits.uop.pdest
145    rfWrite.data := x.bits.data
146    rfWrite
147  }
148
149  intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite)
150  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
151
152  rename.io.wbIntResults <> wbIntResults
153  rename.io.wbFpResults <> wbFpResults
154
155  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
156  roq.io.exeWbResults.last := brq.io.out
157
158
159  // TODO: Remove sink and source
160  val tmp = WireInit(0.U)
161  val sinks = Array[String](
162    "DTLBFINISH",
163    "DTLBPF",
164    "DTLBENABLE",
165    "perfCntCondMdcacheLoss",
166    "perfCntCondMl2cacheLoss",
167    "perfCntCondMdcacheHit",
168    "lsuMMIO",
169    "perfCntCondMl2cacheHit",
170    "perfCntCondMl2cacheReq",
171    "mtip",
172    "perfCntCondMdcacheReq",
173    "meip"
174  )
175  for (s <- sinks){ BoringUtils.addSink(tmp, s) }
176
177  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
178  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
179  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
180  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
181  if(!p.FPGAPlatform){
182    BoringUtils.addSource(debugArchReg, "difftestRegs")
183  }
184
185}
186