xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision bf9968b29deaf6ddc4cc0defed7b216d758fe67d) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.fu.FunctionUnit
15import xiangshan.backend.issue.IssueQueue
16import xiangshan.backend.regfile.{Regfile, RfWritePort}
17import xiangshan.backend.roq.Roq
18
19
20/** Backend Pipeline:
21  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
22  */
23class Backend(implicit val p: XSConfig) extends XSModule
24  with NeedImpl {
25  val io = IO(new Bundle {
26    val dmem = new SimpleBusUC(addrBits = VAddrBits)
27    val memMMU = Flipped(new MemMMUIO)
28    val frontend = Flipped(new FrontendToBackendIO)
29  })
30
31
32  val aluExeUnits = Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
33  val jmpExeUnit = Module(new JmpExeUnit)
34  val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit))
35  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
36  //  val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac))
37  //  val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
38  //  val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
39  val lsuExeUnits = Array.tabulate(exuParameters.StuCnt)(_ => Module(new LsExeUnit))
40  val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits ++ lsuExeUnits)
41  exeUnits.foreach(_.io.exception := DontCare)
42  exeUnits.foreach(_.io.dmem := DontCare)
43  exeUnits.foreach(_.io.scommit := DontCare)
44
45  val decode = Module(new DecodeStage)
46  val brq = Module(new Brq)
47  val decBuf = Module(new DecodeBuffer)
48  val rename = Module(new Rename)
49  val dispatch = Module(new Dispatch(exeUnits.map(_.config)))
50  val roq = Module(new Roq)
51  val intRf = Module(new Regfile(
52    numReadPorts = NRReadPorts,
53    numWirtePorts = NRWritePorts,
54    hasZero = true
55  ))
56  val fpRf = Module(new Regfile(
57    numReadPorts = NRReadPorts,
58    numWirtePorts = NRWritePorts,
59    hasZero = false
60  ))
61
62  // backend redirect, flush pipeline
63  val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect)
64
65  val redirectInfo = Wire(new RedirectInfo)
66  // exception or misprediction
67  redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid
68  redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid
69  redirectInfo.redirect := redirect.bits
70
71  var iqInfo = new StringBuilder
72  val issueQueues = exeUnits.zipWithIndex.map({ case (eu, i) =>
73    def needBypass(cfg: ExuConfig): Boolean = cfg.enableBypass
74
75    val bypassCnt = exeUnits.map(_.config).count(needBypass)
76    def needWakeup(cfg: ExuConfig): Boolean =
77      (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf)
78
79    val wakeupCnt = exeUnits.map(_.config).count(needWakeup)
80    assert(!(needBypass(eu.config) && !needWakeup(eu.config))) // needBypass but dont needWakeup is not allowed
81    val iq = Module(new IssueQueue(
82      eu.config,
83      wakeupCnt,
84      bypassCnt,
85      eu.config.enableBypass,
86      fifo = eu.config.supportedFuncUnits.contains(FunctionUnit.lsuCfg)
87    ))
88    iq.io.redirect <> redirect
89    iq.io.numExist <> dispatch.io.numExist(i)
90    iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
91    iq.io.enqData <> dispatch.io.enqIQData(i)
92    for(
93      (wakeUpPort, exuOut) <-
94      iq.io.wakeUpPorts.zip(exeUnits.filter(e => needWakeup(e.config)).map(_.io.out))
95    ){
96      wakeUpPort.bits := exuOut.bits
97      wakeUpPort.valid := exuOut.valid
98    }
99    iqInfo ++= {
100      s"[$i] ${eu.name} Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt" +
101        s" Supported Function:[" +
102        s"${
103          eu.config.supportedFuncUnits.map(
104            fu => FuType.functionNameMap(fu.fuType.litValue())).mkString(", "
105          )
106        }]\n"
107    }
108    eu.io.in <> iq.io.deq
109    eu.io.redirect <> redirect
110    iq
111  })
112
113  val bypassQueues = issueQueues.filter(_.enableBypass)
114  val bypassUnits = exeUnits.filter(_.config.enableBypass)
115  issueQueues.foreach(iq => {
116    for (i <- iq.io.bypassUops.indices) {
117      iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits
118      iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid
119    }
120    iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop)
121  })
122
123  lsuExeUnits.foreach(_.io.dmem <> io.dmem)
124  lsuExeUnits.foreach(_.io.scommit <> roq.io.scommit)
125  jmpExeUnit.io.exception.valid := roq.io.redirect.valid
126  jmpExeUnit.io.exception.bits := roq.io.exception
127
128  io.frontend.redirectInfo <> redirectInfo
129  io.frontend.commits <> roq.io.commits
130
131  decode.io.in <> io.frontend.cfVec
132  brq.io.roqRedirect <> roq.io.redirect
133  brq.io.enqReqs <> decode.io.toBrq
134  for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) {
135    x.bits := y.io.out.bits
136    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
137  }
138  decode.io.brTags <> brq.io.brTags
139  decBuf.io.redirect <> redirect
140  decBuf.io.in <> decode.io.out
141
142  rename.io.redirect <> redirect
143  rename.io.roqCommits <> roq.io.commits
144  rename.io.in <> decBuf.io.out
145  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr)
146  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr)
147  rename.io.intPregRdy <> dispatch.io.intPregRdy
148  rename.io.fpPregRdy <> dispatch.io.fpPregRdy
149
150  dispatch.io.redirect <> redirect
151  dispatch.io.fromRename <> rename.io.out
152
153  roq.io.brqRedirect <> brq.io.redirect
154  roq.io.dp1Req <> dispatch.io.toRoq
155  dispatch.io.roqIdxs <> roq.io.roqIdxs
156
157  intRf.io.readPorts <> dispatch.io.readIntRf
158  fpRf.io.readPorts <> dispatch.io.readFpRf
159
160  val exeWbReqs = exeUnits.map(_.io.out)
161
162  val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.config.writeIntRf).map(_._2)
163  val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.config.writeFpRf).map(_._2)
164
165  val wbu = Module(new Wbu(wbIntIdx, wbFpIdx))
166  wbu.io.in <> exeWbReqs
167
168  val wbIntResults = wbu.io.toIntRf
169  val wbFpResults = wbu.io.toFpRf
170
171  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
172    val rfWrite = Wire(new RfWritePort)
173    rfWrite.wen := x.valid
174    rfWrite.addr := x.bits.uop.pdest
175    rfWrite.data := x.bits.data
176    rfWrite
177  }
178
179  intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite)
180  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
181
182  rename.io.wbIntResults <> wbIntResults
183  rename.io.wbFpResults <> wbFpResults
184
185  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
186  roq.io.exeWbResults.last := brq.io.out
187
188
189  // TODO: Remove sink and source
190  val tmp = WireInit(0.U)
191  val sinks = Array[String](
192    "DTLBFINISH",
193    "DTLBPF",
194    "DTLBENABLE",
195    "perfCntCondMdcacheLoss",
196    "perfCntCondMl2cacheLoss",
197    "perfCntCondMdcacheHit",
198    "lsuMMIO",
199    "perfCntCondMl2cacheHit",
200    "perfCntCondMl2cacheReq",
201    "mtip",
202    "perfCntCondMdcacheReq",
203    "meip"
204  )
205  for (s <- sinks) {
206    BoringUtils.addSink(tmp, s)
207  }
208
209  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
210  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
211  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
212  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
213  if (!p.FPGAPlatform) {
214    BoringUtils.addSource(debugArchReg, "difftestRegs")
215  }
216
217  print(iqInfo)
218
219}
220