1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ 9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 10import xiangshan.backend.rename.Rename 11import xiangshan.backend.brq.Brq 12import xiangshan.backend.dispatch.Dispatch 13import xiangshan.backend.exu._ 14import xiangshan.backend.fu.FunctionUnit 15import xiangshan.backend.issue.IssueQueue 16import xiangshan.backend.regfile.{Regfile, RfWritePort} 17import xiangshan.backend.roq.Roq 18 19 20/** Backend Pipeline: 21 * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe 22 */ 23class Backend(implicit val p: XSConfig) extends XSModule 24 with HasExeUnits 25 with NeedImpl { 26 val io = IO(new Bundle { 27 val dmem = new SimpleBusUC(addrBits = VAddrBits) 28 val memMMU = Flipped(new MemMMUIO) 29 val frontend = Flipped(new FrontendToBackendIO) 30 }) 31 32 33 val decode = Module(new DecodeStage) 34 val brq = Module(new Brq) 35 val decBuf = Module(new DecodeBuffer) 36 val rename = Module(new Rename) 37 val dispatch = Module(new Dispatch) 38 val roq = Module(new Roq) 39 val intRf = Module(new Regfile( 40 numReadPorts = NRReadPorts, 41 numWirtePorts = NRWritePorts, 42 hasZero = true 43 )) 44 val fpRf = Module(new Regfile( 45 numReadPorts = NRReadPorts, 46 numWirtePorts = NRWritePorts, 47 hasZero = false 48 )) 49 50 // backend redirect, flush pipeline 51 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect) 52 53 val redirectInfo = Wire(new RedirectInfo) 54 // exception or misprediction 55 redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid 56 redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid 57 redirectInfo.redirect := redirect.bits 58 59 val issueQueues = exeUnits.zipWithIndex.map({ case (eu, i) => 60 def needBypass(x: Exu): Boolean = x.enableBypass 61 62 val bypassCnt = if(eu.enableBypass) exeUnits.count(needBypass) else 0 63 def needWakeup(x: Exu): Boolean = (eu.readIntRf && x.writeIntRf) || (eu.readFpRf && x.writeFpRf) 64 65 val wakeupCnt = exeUnits.count(needWakeup) 66 assert(!(needBypass(eu) && !needWakeup(eu))) // needBypass but dont needWakeup is not allowed 67 val iq = Module(new IssueQueue( 68 eu, 69 wakeupCnt, 70 bypassCnt, 71 fifo = eu.supportedFuncUnits.contains(FunctionUnit.lsuCfg) 72 )) 73 iq.io.redirect <> redirect 74 iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i) 75 iq.io.enqData <> dispatch.io.enqIQData(i) 76 val wuUnitsOut = exeUnits.filter(e => needWakeup(e)).map(_.io.out) 77 for (i <- iq.io.wakeUpPorts.indices) { 78 iq.io.wakeUpPorts(i).bits <> wuUnitsOut(i).bits 79 iq.io.wakeUpPorts(i).valid := wuUnitsOut(i).valid 80 } 81 println( 82 s"[$i] ${eu.name} Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt" + 83 s" Supported Function:[" + 84 s"${eu.supportedFuncUnits.map(fu => FuType.functionNameMap(fu.fuType.litValue())).mkString(", ")}]" 85 ) 86 eu.io.in <> iq.io.deq 87 eu.io.redirect <> redirect 88 iq 89 }) 90 91 val bypassQueues = issueQueues.filter(_.bypassCnt > 0) 92 val bypassUnits = exeUnits.filter(_.enableBypass) 93 bypassQueues.foreach(iq => { 94 for (i <- iq.io.bypassUops.indices) { 95 iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits 96 iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid 97 } 98 iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop) 99 }) 100 101 lsuExeUnits.foreach(_.io.dmem <> io.dmem) 102 lsuExeUnits.foreach(_.io.scommit <> roq.io.scommit) 103 104 io.frontend.redirectInfo <> redirectInfo 105 io.frontend.commits <> roq.io.commits 106 107 decode.io.in <> io.frontend.cfVec 108 brq.io.roqRedirect <> roq.io.redirect 109 brq.io.enqReqs <> decode.io.toBrq 110 for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.hasRedirect))) { 111 x.bits := y.io.out.bits 112 x.valid := y.io.out.fire() && y.io.out.bits.redirectValid 113 } 114 decode.io.brTags <> brq.io.brTags 115 decBuf.io.redirect <> redirect 116 decBuf.io.in <> decode.io.out 117 118 rename.io.redirect <> redirect 119 rename.io.roqCommits <> roq.io.commits 120 rename.io.in <> decBuf.io.out 121 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 122 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 123 rename.io.intPregRdy <> dispatch.io.intPregRdy 124 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 125 126 dispatch.io.redirect <> redirect 127 dispatch.io.fromRename <> rename.io.out 128 129 roq.io.brqRedirect <> brq.io.redirect 130 roq.io.dp1Req <> dispatch.io.toRoq 131 dispatch.io.roqIdxs <> roq.io.roqIdxs 132 133 intRf.io.readPorts <> dispatch.io.readIntRf 134 fpRf.io.readPorts <> dispatch.io.readFpRf 135 136 val exeWbReqs = exeUnits.map(_.io.out) 137 138 val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.writeIntRf).map(_._2) 139 val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.writeFpRf).map(_._2) 140 141 val wbu = Module(new Wbu(wbIntIdx, wbFpIdx)) 142 wbu.io.in <> exeWbReqs 143 144 val wbIntResults = wbu.io.toIntRf 145 val wbFpResults = wbu.io.toFpRf 146 147 def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = { 148 val rfWrite = Wire(new RfWritePort) 149 rfWrite.wen := x.valid 150 rfWrite.addr := x.bits.uop.pdest 151 rfWrite.data := x.bits.data 152 rfWrite 153 } 154 155 intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite) 156 fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite) 157 158 rename.io.wbIntResults <> wbIntResults 159 rename.io.wbFpResults <> wbFpResults 160 161 roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2) 162 roq.io.exeWbResults.last := brq.io.out 163 164 165 // TODO: Remove sink and source 166 val tmp = WireInit(0.U) 167 val sinks = Array[String]( 168 "DTLBFINISH", 169 "DTLBPF", 170 "DTLBENABLE", 171 "perfCntCondMdcacheLoss", 172 "perfCntCondMl2cacheLoss", 173 "perfCntCondMdcacheHit", 174 "lsuMMIO", 175 "perfCntCondMl2cacheHit", 176 "perfCntCondMl2cacheReq", 177 "mtip", 178 "perfCntCondMdcacheReq", 179 "meip" 180 ) 181 for (s <- sinks) { 182 BoringUtils.addSink(tmp, s) 183 } 184 185 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 186 BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG") 187 BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG") 188 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 189 if (!p.FPGAPlatform) { 190 BoringUtils.addSource(debugArchReg, "difftestRegs") 191 } 192 193} 194