backend: merge v2backend into backend

backend,Core: remove dead code and comments

DataPath: add regfile read arbiter

backend: add float inst support

func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028)

* func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN

* pom(yunsuan): add isVsild

func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN (#2028)

* func(UopDivType): support VEC_SLIDEUP/VEC_ISLIDEUP/VEC_SLIDEDOWN/VEC_ISLIDEDOWN

* pom(yunsuan): add isVsilde in VpermType & fix bugs of Permutation

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backend: refactor regfile rw parameters

* support float memory load/store
* refactor regfile read parameters
* replace `numSrc` with `numRegSrc` to notice the src data being from regfile
* refacto

backend: refactor regfile rw parameters

* support float memory load/store
* refactor regfile read parameters
* replace `numSrc` with `numRegSrc` to notice the src data being from regfile
* refactor BusyTable read port
* make int/vf BusyTable have the same number of read ports to simplify connection in Dispatch2Iq
* the unused read port will be optimized
* regular IQSize parameters
* split writeback port for scheduler into two kinds by reg types

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func(DecodeUnitComp): support VEC_VRED (#2017)

* func(DecodeUnitComp): support VEC_VRED of UopDivType

* fix(vxsat):fix bug that VPU's vxsat shout be arbitrated

* pom(yunsuan):fix Decode of vmvsx &

func(DecodeUnitComp): support VEC_VRED (#2017)

* func(DecodeUnitComp): support VEC_VRED of UopDivType

* fix(vxsat):fix bug that VPU's vxsat shout be arbitrated

* pom(yunsuan):fix Decode of vmvsx & add some test for VPERM

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func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012)

* func(DecodeUnitComp): support vfslide1up.vf

* func(DecodeUnitComp):support vslide1down & vfslide1down

* pom(yunsuan

func(DecodeUnitComp) : support vfslide1up & vslide1down & vfslide1down (#2012)

* func(DecodeUnitComp): support vfslide1up.vf

* func(DecodeUnitComp):support vslide1down & vfslide1down

* pom(yunsuan):add vfslide1up & vfslide1down

1. func(VFMA):add vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub, vfwmul, vfwmacc, vfwnmacc, vfwmsac, vfwnmsac and their test supports
2. func(VpermType): add vfslide1up & vfslide1down

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backend: add load inst support

ICache: IPrefetchEntries 2 -> 12 & use dcache aliasOptBit

Merge branch 'master' into fdip-icache-migrate

fix(vset): fix vset bug that writing vconfig need the condition of rfWen==true (#1982)

Fix replay logic in unified load queue (#1966)

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use c

Fix replay logic in unified load queue (#1966)

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use counter to delay)
* if dcache's mshr gets refill data, wake up lq's missed load
* uncache load will writeback to ldu using ldout_0
* ldout_1 is no longer used

* lq, ldu: add forward port

* forward D and mshr in load S1, get result in S2
* remove useless code logic in loadQueueData

* misc: revert monitor

* lq: change replay cycle

* lq: change replay cycle
* change cycle to 11 36 10 10

* Revert "lq: change replay cycle"

This reverts commit 3ca74b63eaeef7792016cd270b77f8a14f588981.
And change replay cycles

* lq: change replay cycle according to dramsim

* change Reselectlen to 7
* change replay cycle to (11, 18, 127, 17) to fit refill delay (14, 36,
188)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 32, 51)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 126, 95)

* lq: fix replay ptr update logic

* fix priority of updating ptr
* revert block_cycles_cache

* lq: change tlb replay cycle

* change tlbReplayDelayCycleCtrl to (15, 0, 126, 0)

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decode: fix narrowing instrutions bugs(uop-div) (#1972)

debug: fix some bugs (#1968)

1. fix vset related bugs
2. modifiy the update logic of vxsat
3. modify numFpRfPorts parameter in the ReservationStationBase

<revert> ICache: nPerfetchEntrys 12 -> 2

Rob: Add Rab module to support separate commit of uops and instructions (#1956)

ICache: nPrefetchEntrys 2 -> 12

decode: modify vx instruction uops and fix bug (#1952)

v2backend: huge tmp commit

ICache:finish migrate fdip from branch <kmh-fdip>

Merge remote-tracking branch 'origin/master' into rf-after-issue

TLB: Prefetch TLB will not do difftest check (#1923)

param: set EnableUncacheWriteOutstanding to false (#1913)

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
clear intrGen's intr: S

param: set EnableUncacheWriteOutstanding to false (#1913)

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
clear intrGen's intr: Stop pass interrupt. A mmio write.
clear plic claim: complete intr. A mmio write.
read plic claim to check: claim should be 0. A mmio read.
The corner case:
intrGen's mmio write is to slow. The instruction after it executes
and plic claim's mmio's write & read execute before it. On the side of
core with plic, claim is cleared. But on the side of intrGen with plic,
the source of interrupt is still enabled and trigger interrupt.
So the "read plic claim to check" get a valid claim and failed.

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param: set EnableUncacheWriteOutstanding to false

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
clear intrGen's intr: Stop pass in

param: set EnableUncacheWriteOutstanding to false

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
clear intrGen's intr: Stop pass interrupt. A mmio write.
clear plic claim: complete intr. A mmio write.
read plic claim to check: claim should be 0. A mmio read.
The corner case:
intrGen's mmio write is to slow. The instruction after it executes
and plic claim's mmio's write & read execute before it. On the side of
core with plic, claim is cleared. But on the side of intrGen with plic,
the source of interrupt is still enabled and trigger interrupt.
So the "read plic claim to check" get a valid claim and failed.

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