1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import huancun.debug._ 24import system.SoCParamsKey 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.backend.exu._ 27import xiangshan.cache.DCacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import xiangshan.cache.prefetch._ 30import xiangshan.frontend._ 31import xiangshan.frontend.icache.ICacheParameters 32import xiangshan.v2backend._ 33 34import scala.math.min 35 36case object XSTileKey extends Field[Seq[XSCoreParameters]] 37 38case object XSCoreParamsKey extends Field[XSCoreParameters] 39 40case class XSCoreParameters 41( 42 HasPrefetch: Boolean = false, 43 HartId: Int = 0, 44 XLEN: Int = 64, 45 VLEN: Int = 128, 46 HasMExtension: Boolean = true, 47 HasCExtension: Boolean = true, 48 HasDiv: Boolean = true, 49 HasICache: Boolean = true, 50 HasDCache: Boolean = true, 51 AddrBits: Int = 64, 52 VAddrBits: Int = 39, 53 HasFPU: Boolean = true, 54 HasVPU: Boolean = true, 55 HasCustomCSRCacheOp: Boolean = true, 56 FetchWidth: Int = 8, 57 AsidLength: Int = 16, 58 EnableBPU: Boolean = true, 59 EnableBPD: Boolean = true, 60 EnableRAS: Boolean = true, 61 EnableLB: Boolean = false, 62 EnableLoop: Boolean = true, 63 EnableSC: Boolean = true, 64 EnbaleTlbDebug: Boolean = false, 65 EnableJal: Boolean = false, 66 EnableFauFTB: Boolean = true, 67 UbtbGHRLength: Int = 4, 68 // HistoryLength: Int = 512, 69 EnableGHistDiff: Boolean = true, 70 UbtbSize: Int = 256, 71 FtbSize: Int = 2048, 72 RasSize: Int = 32, 73 CacheLineSize: Int = 512, 74 FtbWays: Int = 4, 75 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 76 // Sets Hist Tag 77 // Seq(( 2048, 2, 8), 78 // ( 2048, 9, 8), 79 // ( 2048, 13, 8), 80 // ( 2048, 20, 8), 81 // ( 2048, 26, 8), 82 // ( 2048, 44, 8), 83 // ( 2048, 73, 8), 84 // ( 2048, 256, 8)), 85 Seq(( 4096, 8, 8), 86 ( 4096, 13, 8), 87 ( 4096, 32, 8), 88 ( 4096, 119, 8)), 89 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 90 // Sets Hist Tag 91 Seq(( 256, 4, 9), 92 ( 256, 8, 9), 93 ( 512, 13, 9), 94 ( 512, 16, 9), 95 ( 512, 32, 9)), 96 SCNRows: Int = 512, 97 SCNTables: Int = 4, 98 SCCtrBits: Int = 6, 99 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 100 numBr: Int = 2, 101 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 102 ((resp_in: BranchPredictionResp, p: Parameters) => { 103 val ftb = Module(new FTB()(p)) 104 val ubtb =Module(new FauFTB()(p)) 105 // val bim = Module(new BIM()(p)) 106 val tage = Module(new Tage_SC()(p)) 107 val ras = Module(new RAS()(p)) 108 val ittage = Module(new ITTage()(p)) 109 val preds = Seq(ubtb, tage, ftb, ittage, ras) 110 preds.map(_.io := DontCare) 111 112 // ubtb.io.resp_in(0) := resp_in 113 // bim.io.resp_in(0) := ubtb.io.resp 114 // btb.io.resp_in(0) := bim.io.resp 115 // tage.io.resp_in(0) := btb.io.resp 116 // loop.io.resp_in(0) := tage.io.resp 117 ubtb.io.in.bits.resp_in(0) := resp_in 118 tage.io.in.bits.resp_in(0) := ubtb.io.out 119 ftb.io.in.bits.resp_in(0) := tage.io.out 120 ittage.io.in.bits.resp_in(0) := ftb.io.out 121 ras.io.in.bits.resp_in(0) := ittage.io.out 122 123 (preds, ras.io.out) 124 }), 125 IBufSize: Int = 48, 126 DecodeWidth: Int = 6, 127 RenameWidth: Int = 6, 128 CommitWidth: Int = 6, 129 FtqSize: Int = 64, 130 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 131 IssQueSize: Int = 16, 132 NRPhyRegs: Int = 192, 133 IntPhyRegs: Int = 192, 134 VfPhyRegs: Int = 192, 135 LoadQueueSize: Int = 80, 136 LoadQueueNWriteBanks: Int = 8, 137 StoreQueueSize: Int = 64, 138 StoreQueueNWriteBanks: Int = 8, 139 VlsQueueSize: Int = 8, 140 RobSize: Int = 256, 141 dpParams: DispatchParameters = DispatchParameters( 142 IntDqSize = 16, 143 FpDqSize = 16, 144 LsDqSize = 16, 145 IntDqDeqWidth = 6, 146 FpDqDeqWidth = 6, 147 LsDqDeqWidth = 6, 148 ), 149 intPreg: PregParams = IntPregParams( 150 numEntries = 64, 151 numRead = 14, 152 numWrite = 8, 153 ), 154 vfPreg: VfPregParams = VfPregParams( 155 numEntries = 64, 156 numRead = 14, 157 numWrite = 8, 158 ), 159// exuParameters: ExuParameters = ExuParameters( 160// JmpCnt = 1, 161// AluCnt = 4, 162// MulCnt = 0, 163// MduCnt = 2, 164// FmacCnt = 4, 165// FmiscCnt = 2, 166// FmiscDivSqrtCnt = 0, 167// LduCnt = 2, 168// StuCnt = 2 169// ), 170 LoadPipelineWidth: Int = 2, 171 StorePipelineWidth: Int = 2, 172 VecMemSrcInWidth: Int = 2, 173 VecMemInstWbWidth: Int = 1, 174 VecMemDispatchWidth: Int = 1, 175 StoreBufferSize: Int = 16, 176 StoreBufferThreshold: Int = 7, 177 EnsbufferWidth: Int = 2, 178 UncacheBufferSize: Int = 4, 179 EnableLoadToLoadForward: Boolean = true, 180 EnableFastForward: Boolean = false, 181 EnableLdVioCheckAfterReset: Boolean = true, 182 EnableSoftPrefetchAfterReset: Boolean = true, 183 EnableCacheErrorAfterReset: Boolean = true, 184 EnableDCacheWPU: Boolean = false, 185 EnableAccurateLoadError: Boolean = true, 186 EnableUncacheWriteOutstanding: Boolean = true, 187 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 188 ReSelectLen: Int = 6, // load replay queue replay select counter len 189 itlbParameters: TLBParameters = TLBParameters( 190 name = "itlb", 191 fetchi = true, 192 useDmode = false, 193 normalNWays = 32, 194 normalReplacer = Some("plru"), 195 superNWays = 4, 196 superReplacer = Some("plru") 197 ), 198 ldtlbParameters: TLBParameters = TLBParameters( 199 name = "ldtlb", 200 normalNSets = 64, 201 normalNWays = 1, 202 normalAssociative = "sa", 203 normalReplacer = Some("setplru"), 204 superNWays = 16, 205 normalAsVictim = true, 206 outReplace = false, 207 partialStaticPMP = true, 208 outsideRecvFlush = true, 209 saveLevel = true 210 ), 211 sttlbParameters: TLBParameters = TLBParameters( 212 name = "sttlb", 213 normalNSets = 64, 214 normalNWays = 1, 215 normalAssociative = "sa", 216 normalReplacer = Some("setplru"), 217 superNWays = 16, 218 normalAsVictim = true, 219 outReplace = false, 220 partialStaticPMP = true, 221 outsideRecvFlush = true, 222 saveLevel = true 223 ), 224 refillBothTlb: Boolean = false, 225 btlbParameters: TLBParameters = TLBParameters( 226 name = "btlb", 227 normalNSets = 1, 228 normalNWays = 64, 229 superNWays = 4, 230 ), 231 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 232 NumPerfCounters: Int = 16, 233 icacheParameters: ICacheParameters = ICacheParameters( 234 tagECC = Some("parity"), 235 dataECC = Some("parity"), 236 replacer = Some("setplru"), 237 nMissEntries = 2, 238 nProbeEntries = 2, 239 nPrefetchEntries = 2, 240 hasPrefetch = true, 241 ), 242 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 243 tagECC = Some("secded"), 244 dataECC = Some("secded"), 245 replacer = Some("setplru"), 246 nMissEntries = 16, 247 nProbeEntries = 8, 248 nReleaseEntries = 18 249 )), 250 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 251 name = "l2", 252 level = 2, 253 ways = 8, 254 sets = 1024, // default 512KB L2 255 prefetch = Some(huancun.prefetch.BOPParameters()) 256 )), 257 L2NBanks: Int = 1, 258 usePTWRepeater: Boolean = false, 259 softPTW: Boolean = false, // dpi-c debug only 260 softPTWDelay: Int = 1 261){ 262 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 263 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 264 265 def intSchdParams = { 266 implicit val schdType: SchedulerType = IntScheduler() 267 val pregBits = intPreg.addrWidth 268 val numRfRead = intPreg.numRead 269 val numRfWrite = intPreg.numWrite 270 SchdBlockParams(Seq( 271 IssueBlockParams(Seq( 272 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0))), 273 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0))), 274 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 275 IssueBlockParams(Seq( 276 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0))), 277 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0))), 278 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 279 IssueBlockParams(Seq( 280 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0))), 281 ExeUnitParams(Seq(BrhCfg), Seq()), 282 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 283 IssueBlockParams(Seq( 284 ExeUnitParams(Seq(I2fCfg), Seq(VecWB(port = 6, Int.MaxValue))), 285 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 286 ), 287 numPregs = intPreg.numEntries, 288 numRfReadWrite = Some((numRfRead, numRfWrite)), 289 numDeqOutside = 0, 290 schdType = schdType, 291 rfDataWidth = intPreg.dataCfg.dataWidth, 292 numUopIn = dpParams.IntDqDeqWidth, 293 ) 294 } 295 def vfSchdParams = { 296 implicit val schdType: SchedulerType = VfScheduler() 297 val pregBits = vfPreg.addrWidth 298 val numRfRead = vfPreg.numRead 299 val numRfWrite = vfPreg.numWrite 300 SchdBlockParams(Seq( 301 IssueBlockParams(Seq( 302 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 0, 0))), 303 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0))), 304 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 305 IssueBlockParams(Seq( 306 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0))), 307 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 308 ), 309 numPregs = vfPreg.numEntries, 310 numRfReadWrite = Some((numRfRead, numRfWrite)), 311 numDeqOutside = 0, 312 schdType = schdType, 313 rfDataWidth = vfPreg.dataCfg.dataWidth, 314 numUopIn = dpParams.FpDqDeqWidth, 315 ) 316 } 317 def memSchdParams = { 318 implicit val schdType: SchedulerType = MemScheduler() 319 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 320 val rfDataWidth = 64 321 322 SchdBlockParams(Seq( 323 IssueBlockParams(Seq( 324 ExeUnitParams(Seq(LduCfg), WBSeq(IntWB(5, 0), VecWB(4, 0))), 325 ExeUnitParams(Seq(LduCfg), WBSeq(IntWB(6, 0), VecWB(5, 0))), 326 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 327 IssueBlockParams(Seq( 328 ExeUnitParams(Seq(StaCfg), WBSeq()), 329 ExeUnitParams(Seq(StaCfg), WBSeq()), 330 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 331 IssueBlockParams(Seq( 332 ExeUnitParams(Seq(StdCfg), WBSeq()), 333 ExeUnitParams(Seq(StdCfg), WBSeq()), 334 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 335 ), 336 numPregs = intPreg.numEntries max vfPreg.numEntries, 337 numRfReadWrite = None, 338 numDeqOutside = 0, 339 schdType = schdType, 340 rfDataWidth = rfDataWidth, 341 numUopIn = dpParams.LsDqDeqWidth, 342 ) 343 } 344 345 def backendParams: BackendParams = BackendParams(Map( 346 IntScheduler() -> intSchdParams, 347 VfScheduler() -> vfSchdParams, 348 MemScheduler() -> memSchdParams, 349 ), Seq( 350 intPreg, 351 vfPreg, 352 )) 353} 354 355case object DebugOptionsKey extends Field[DebugOptions] 356 357case class DebugOptions 358( 359 FPGAPlatform: Boolean = false, 360 EnableDifftest: Boolean = false, 361 AlwaysBasicDiff: Boolean = true, 362 EnableDebug: Boolean = false, 363 EnablePerfDebug: Boolean = true, 364 UseDRAMSim: Boolean = false, 365 EnableTopDown: Boolean = false 366) 367 368trait HasXSParameter { 369 370 implicit val p: Parameters 371 372 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 373 374 val coreParams = p(XSCoreParamsKey) 375 val env = p(DebugOptionsKey) 376 377 val XLEN = coreParams.XLEN 378 val VLEN = coreParams.VLEN 379 val minFLen = 32 380 val fLen = 64 381 def xLen = XLEN 382 383 val HasMExtension = coreParams.HasMExtension 384 val HasCExtension = coreParams.HasCExtension 385 val HasDiv = coreParams.HasDiv 386 val HasIcache = coreParams.HasICache 387 val HasDcache = coreParams.HasDCache 388 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 389 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 390 val AsidLength = coreParams.AsidLength 391 val ReSelectLen = coreParams.ReSelectLen 392 val AddrBytes = AddrBits / 8 // unused 393 val DataBits = XLEN 394 val DataBytes = DataBits / 8 395 val HasFPU = coreParams.HasFPU 396 val HasVPU = coreParams.HasVPU 397 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 398 val FetchWidth = coreParams.FetchWidth 399 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 400 val EnableBPU = coreParams.EnableBPU 401 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 402 val EnableRAS = coreParams.EnableRAS 403 val EnableLB = coreParams.EnableLB 404 val EnableLoop = coreParams.EnableLoop 405 val EnableSC = coreParams.EnableSC 406 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 407 val HistoryLength = coreParams.HistoryLength 408 val EnableGHistDiff = coreParams.EnableGHistDiff 409 val UbtbGHRLength = coreParams.UbtbGHRLength 410 val UbtbSize = coreParams.UbtbSize 411 val EnableFauFTB = coreParams.EnableFauFTB 412 val FtbSize = coreParams.FtbSize 413 val FtbWays = coreParams.FtbWays 414 val RasSize = coreParams.RasSize 415 416 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 417 coreParams.branchPredictor(resp_in, p) 418 } 419 val numBr = coreParams.numBr 420 val TageTableInfos = coreParams.TageTableInfos 421 val TageBanks = coreParams.numBr 422 val SCNRows = coreParams.SCNRows 423 val SCCtrBits = coreParams.SCCtrBits 424 val SCHistLens = coreParams.SCHistLens 425 val SCNTables = coreParams.SCNTables 426 427 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 428 case ((n, cb), h) => (n, cb, h) 429 } 430 val ITTageTableInfos = coreParams.ITTageTableInfos 431 type FoldedHistoryInfo = Tuple2[Int, Int] 432 val foldedGHistInfos = 433 (TageTableInfos.map{ case (nRows, h, t) => 434 if (h > 0) 435 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 436 else 437 Set[FoldedHistoryInfo]() 438 }.reduce(_++_).toSet ++ 439 SCTableInfos.map{ case (nRows, _, h) => 440 if (h > 0) 441 Set((h, min(log2Ceil(nRows/TageBanks), h))) 442 else 443 Set[FoldedHistoryInfo]() 444 }.reduce(_++_).toSet ++ 445 ITTageTableInfos.map{ case (nRows, h, t) => 446 if (h > 0) 447 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 448 else 449 Set[FoldedHistoryInfo]() 450 }.reduce(_++_) ++ 451 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 452 ).toList 453 454 455 456 val CacheLineSize = coreParams.CacheLineSize 457 val CacheLineHalfWord = CacheLineSize / 16 458 val ExtHistoryLength = HistoryLength + 64 459 val IBufSize = coreParams.IBufSize 460 val DecodeWidth = coreParams.DecodeWidth 461 val RenameWidth = coreParams.RenameWidth 462 val CommitWidth = coreParams.CommitWidth 463 val FtqSize = coreParams.FtqSize 464 val IssQueSize = coreParams.IssQueSize 465 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 466 val NRPhyRegs = coreParams.NRPhyRegs 467 val PhyRegIdxWidth = log2Up(NRPhyRegs) 468 val IntPhyRegs = coreParams.IntPhyRegs 469 val VfPhyRegs = coreParams.VfPhyRegs 470 val IntPregIdxWidth = log2Up(IntPhyRegs) 471 val VfPregIdxWidth = log2Up(VfPhyRegs) 472 val RobSize = coreParams.RobSize 473 val IntRefCounterWidth = log2Ceil(RobSize) 474 val LoadQueueSize = coreParams.LoadQueueSize 475 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 476 val StoreQueueSize = coreParams.StoreQueueSize 477 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 478 val VlsQueueSize = coreParams.VlsQueueSize 479 val dpParams = coreParams.dpParams 480 481 def backendParams: BackendParams = coreParams.backendParams 482 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 483 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 484// val exuParameters = coreParams.exuParameters 485// val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 486// val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 487// val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 488// val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 489// val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 490 val LoadPipelineWidth = coreParams.LoadPipelineWidth 491 val StorePipelineWidth = coreParams.StorePipelineWidth 492 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 493 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 494 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 495 val StoreBufferSize = coreParams.StoreBufferSize 496 val StoreBufferThreshold = coreParams.StoreBufferThreshold 497 val EnsbufferWidth = coreParams.EnsbufferWidth 498 val UncacheBufferSize = coreParams.UncacheBufferSize 499 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 500 val EnableFastForward = coreParams.EnableFastForward 501 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 502 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 503 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 504 val EnableDCacheWPU = coreParams.EnableDCacheWPU 505 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 506 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 507 val asidLen = coreParams.MMUAsidLen 508 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 509 val refillBothTlb = coreParams.refillBothTlb 510 val itlbParams = coreParams.itlbParameters 511 val ldtlbParams = coreParams.ldtlbParameters 512 val sttlbParams = coreParams.sttlbParameters 513 val btlbParams = coreParams.btlbParameters 514 val l2tlbParams = coreParams.l2tlbParameters 515 val NumPerfCounters = coreParams.NumPerfCounters 516 517// val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 518// (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 519// (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 520// (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 521 522 val instBytes = if (HasCExtension) 2 else 4 523 val instOffsetBits = log2Ceil(instBytes) 524 525 val icacheParameters = coreParams.icacheParameters 526 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 527 528 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 529 // for constrained LR/SC loop 530 val LRSCCycles = 64 531 // for lr storm 532 val LRSCBackOff = 8 533 534 // cache hierarchy configurations 535 val l1BusDataWidth = 256 536 537 // load violation predict 538 val ResetTimeMax2Pow = 20 //1078576 539 val ResetTimeMin2Pow = 10 //1024 540 // wait table parameters 541 val WaitTableSize = 1024 542 val MemPredPCWidth = log2Up(WaitTableSize) 543 val LWTUse2BitCounter = true 544 // store set parameters 545 val SSITSize = WaitTableSize 546 val LFSTSize = 32 547 val SSIDWidth = log2Up(LFSTSize) 548 val LFSTWidth = 4 549 val StoreSetEnable = true // LWT will be disabled if SS is enabled 550 551// val loadExuConfigs = coreParams.loadExuConfigs 552// val storeExuConfigs = coreParams.storeExuConfigs 553// 554// val intExuConfigs = coreParams.intExuConfigs 555// 556// val fpExuConfigs = coreParams.fpExuConfigs 557// 558// val exuConfigs = coreParams.exuConfigs 559 560 val PCntIncrStep: Int = 6 561 val numPCntHc: Int = 25 562 val numPCntPtw: Int = 19 563 564 val numCSRPCntFrontend = 8 565 val numCSRPCntCtrl = 8 566 val numCSRPCntLsu = 8 567 val numCSRPCntHc = 5 568} 569