1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 41case class XSCoreParameters 42( 43 HasPrefetch: Boolean = false, 44 HartId: Int = 0, 45 XLEN: Int = 64, 46 VLEN: Int = 128, 47 HasMExtension: Boolean = true, 48 HasCExtension: Boolean = true, 49 HasDiv: Boolean = true, 50 HasICache: Boolean = true, 51 HasDCache: Boolean = true, 52 AddrBits: Int = 64, 53 VAddrBits: Int = 39, 54 HasFPU: Boolean = true, 55 HasVPU: Boolean = true, 56 HasCustomCSRCacheOp: Boolean = true, 57 FetchWidth: Int = 8, 58 AsidLength: Int = 16, 59 EnableBPU: Boolean = true, 60 EnableBPD: Boolean = true, 61 EnableRAS: Boolean = true, 62 EnableLB: Boolean = false, 63 EnableLoop: Boolean = true, 64 EnableSC: Boolean = true, 65 EnbaleTlbDebug: Boolean = false, 66 EnableJal: Boolean = false, 67 EnableFauFTB: Boolean = true, 68 UbtbGHRLength: Int = 4, 69 // HistoryLength: Int = 512, 70 EnableGHistDiff: Boolean = true, 71 UbtbSize: Int = 256, 72 FtbSize: Int = 2048, 73 RasSize: Int = 32, 74 CacheLineSize: Int = 512, 75 FtbWays: Int = 4, 76 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 77 // Sets Hist Tag 78 // Seq(( 2048, 2, 8), 79 // ( 2048, 9, 8), 80 // ( 2048, 13, 8), 81 // ( 2048, 20, 8), 82 // ( 2048, 26, 8), 83 // ( 2048, 44, 8), 84 // ( 2048, 73, 8), 85 // ( 2048, 256, 8)), 86 Seq(( 4096, 8, 8), 87 ( 4096, 13, 8), 88 ( 4096, 32, 8), 89 ( 4096, 119, 8)), 90 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 Seq(( 256, 4, 9), 93 ( 256, 8, 9), 94 ( 512, 13, 9), 95 ( 512, 16, 9), 96 ( 512, 32, 9)), 97 SCNRows: Int = 512, 98 SCNTables: Int = 4, 99 SCCtrBits: Int = 6, 100 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 101 numBr: Int = 2, 102 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 103 ((resp_in: BranchPredictionResp, p: Parameters) => { 104 val ftb = Module(new FTB()(p)) 105 val ubtb =Module(new FauFTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 val preds = Seq(ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 ubtb.io.in.bits.resp_in(0) := resp_in 119 tage.io.in.bits.resp_in(0) := ubtb.io.out 120 ftb.io.in.bits.resp_in(0) := tage.io.out 121 ittage.io.in.bits.resp_in(0) := ftb.io.out 122 ras.io.in.bits.resp_in(0) := ittage.io.out 123 124 (preds, ras.io.out) 125 }), 126 IBufSize: Int = 48, 127 DecodeWidth: Int = 6, 128 RenameWidth: Int = 6, 129 CommitWidth: Int = 6, 130 MaxUopSize: Int = 37, 131 FtqSize: Int = 64, 132 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 133 IssQueSize: Int = 16, 134 IntLogicRegs: Int = 33, 135 FpLogicRegs: Int = 33, 136 VecLogicRegs: Int = 39, 137 NRPhyRegs: Int = 192, 138 IntPhyRegs: Int = 192, 139 VfPhyRegs: Int = 192, 140 LoadQueueSize: Int = 80, 141 LoadQueueNWriteBanks: Int = 8, 142 StoreQueueSize: Int = 64, 143 StoreQueueNWriteBanks: Int = 8, 144 VlsQueueSize: Int = 8, 145 RobSize: Int = 256, 146 RabSize: Int = 256, 147 dpParams: DispatchParameters = DispatchParameters( 148 IntDqSize = 16, 149 FpDqSize = 16, 150 LsDqSize = 16, 151 IntDqDeqWidth = 4, 152 FpDqDeqWidth = 4, 153 LsDqDeqWidth = 4 154 ), 155 exuParameters: ExuParameters = ExuParameters( 156 JmpCnt = 1, 157 AluCnt = 4, 158 MulCnt = 0, 159 MduCnt = 2, 160 FmacCnt = 4, 161 FmiscCnt = 2, 162 FmiscDivSqrtCnt = 0, 163 LduCnt = 2, 164 StuCnt = 2 165 ), 166 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 167 LoadPipelineWidth: Int = 2, 168 StorePipelineWidth: Int = 2, 169 VecMemSrcInWidth: Int = 2, 170 VecMemInstWbWidth: Int = 1, 171 VecMemDispatchWidth: Int = 1, 172 StoreBufferSize: Int = 16, 173 StoreBufferThreshold: Int = 7, 174 EnsbufferWidth: Int = 2, 175 UncacheBufferSize: Int = 4, 176 EnableLoadToLoadForward: Boolean = true, 177 EnableFastForward: Boolean = false, 178 EnableLdVioCheckAfterReset: Boolean = true, 179 EnableSoftPrefetchAfterReset: Boolean = true, 180 EnableCacheErrorAfterReset: Boolean = true, 181 EnableDCacheWPU: Boolean = false, 182 EnableAccurateLoadError: Boolean = true, 183 EnableUncacheWriteOutstanding: Boolean = false, 184 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 185 ReSelectLen: Int = 6, // load replay queue replay select counter len 186 itlbParameters: TLBParameters = TLBParameters( 187 name = "itlb", 188 fetchi = true, 189 useDmode = false, 190 normalNWays = 32, 191 normalReplacer = Some("plru"), 192 superNWays = 4, 193 superReplacer = Some("plru") 194 ), 195 ldtlbParameters: TLBParameters = TLBParameters( 196 name = "ldtlb", 197 normalNSets = 64, 198 normalNWays = 1, 199 normalAssociative = "sa", 200 normalReplacer = Some("setplru"), 201 superNWays = 16, 202 normalAsVictim = true, 203 outReplace = false, 204 partialStaticPMP = true, 205 outsideRecvFlush = true, 206 saveLevel = true 207 ), 208 sttlbParameters: TLBParameters = TLBParameters( 209 name = "sttlb", 210 normalNSets = 64, 211 normalNWays = 1, 212 normalAssociative = "sa", 213 normalReplacer = Some("setplru"), 214 superNWays = 16, 215 normalAsVictim = true, 216 outReplace = false, 217 partialStaticPMP = true, 218 outsideRecvFlush = true, 219 saveLevel = true 220 ), 221 pftlbParameters: TLBParameters = TLBParameters( 222 name = "pftlb", 223 normalNSets = 64, 224 normalNWays = 1, 225 normalAssociative = "sa", 226 normalReplacer = Some("setplru"), 227 superNWays = 16, 228 normalAsVictim = true, 229 outReplace = false, 230 partialStaticPMP = true, 231 outsideRecvFlush = true, 232 saveLevel = true 233 ), 234 refillBothTlb: Boolean = false, 235 btlbParameters: TLBParameters = TLBParameters( 236 name = "btlb", 237 normalNSets = 1, 238 normalNWays = 64, 239 superNWays = 4, 240 ), 241 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 242 NumPerfCounters: Int = 16, 243 icacheParameters: ICacheParameters = ICacheParameters( 244 tagECC = Some("parity"), 245 dataECC = Some("parity"), 246 replacer = Some("setplru"), 247 nMissEntries = 2, 248 nProbeEntries = 2, 249 nPrefetchEntries = 2, 250 hasPrefetch = true, 251 ), 252 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 253 tagECC = Some("secded"), 254 dataECC = Some("secded"), 255 replacer = Some("setplru"), 256 nMissEntries = 16, 257 nProbeEntries = 8, 258 nReleaseEntries = 18 259 )), 260 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 261 name = "l2", 262 level = 2, 263 ways = 8, 264 sets = 1024, // default 512KB L2 265 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 266 )), 267 L2NBanks: Int = 1, 268 usePTWRepeater: Boolean = false, 269 softTLB: Boolean = false, // dpi-c l1tlb debug only 270 softPTW: Boolean = false, // dpi-c l2tlb debug only 271 softPTWDelay: Int = 1 272){ 273 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 274 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 275 276 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 277 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 278 279 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 280 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 281 282 val fpExuConfigs = 283 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 284 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 285 286 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 287} 288 289case object DebugOptionsKey extends Field[DebugOptions] 290 291case class DebugOptions 292( 293 FPGAPlatform: Boolean = false, 294 EnableDifftest: Boolean = false, 295 AlwaysBasicDiff: Boolean = true, 296 EnableDebug: Boolean = false, 297 EnablePerfDebug: Boolean = true, 298 UseDRAMSim: Boolean = false, 299 EnableTopDown: Boolean = false 300) 301 302trait HasXSParameter { 303 304 implicit val p: Parameters 305 306 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 307 308 val coreParams = p(XSCoreParamsKey) 309 val env = p(DebugOptionsKey) 310 311 val XLEN = coreParams.XLEN 312 val VLEN = coreParams.VLEN 313 val minFLen = 32 314 val fLen = 64 315 def xLen = XLEN 316 317 val HasMExtension = coreParams.HasMExtension 318 val HasCExtension = coreParams.HasCExtension 319 val HasDiv = coreParams.HasDiv 320 val HasIcache = coreParams.HasICache 321 val HasDcache = coreParams.HasDCache 322 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 323 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 324 val AsidLength = coreParams.AsidLength 325 val ReSelectLen = coreParams.ReSelectLen 326 val AddrBytes = AddrBits / 8 // unused 327 val DataBits = XLEN 328 val DataBytes = DataBits / 8 329 val HasFPU = coreParams.HasFPU 330 val HasVPU = coreParams.HasVPU 331 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 332 val FetchWidth = coreParams.FetchWidth 333 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 334 val EnableBPU = coreParams.EnableBPU 335 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 336 val EnableRAS = coreParams.EnableRAS 337 val EnableLB = coreParams.EnableLB 338 val EnableLoop = coreParams.EnableLoop 339 val EnableSC = coreParams.EnableSC 340 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 341 val HistoryLength = coreParams.HistoryLength 342 val EnableGHistDiff = coreParams.EnableGHistDiff 343 val UbtbGHRLength = coreParams.UbtbGHRLength 344 val UbtbSize = coreParams.UbtbSize 345 val EnableFauFTB = coreParams.EnableFauFTB 346 val FtbSize = coreParams.FtbSize 347 val FtbWays = coreParams.FtbWays 348 val RasSize = coreParams.RasSize 349 350 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 351 coreParams.branchPredictor(resp_in, p) 352 } 353 val numBr = coreParams.numBr 354 val TageTableInfos = coreParams.TageTableInfos 355 val TageBanks = coreParams.numBr 356 val SCNRows = coreParams.SCNRows 357 val SCCtrBits = coreParams.SCCtrBits 358 val SCHistLens = coreParams.SCHistLens 359 val SCNTables = coreParams.SCNTables 360 361 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 362 case ((n, cb), h) => (n, cb, h) 363 } 364 val ITTageTableInfos = coreParams.ITTageTableInfos 365 type FoldedHistoryInfo = Tuple2[Int, Int] 366 val foldedGHistInfos = 367 (TageTableInfos.map{ case (nRows, h, t) => 368 if (h > 0) 369 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 370 else 371 Set[FoldedHistoryInfo]() 372 }.reduce(_++_).toSet ++ 373 SCTableInfos.map{ case (nRows, _, h) => 374 if (h > 0) 375 Set((h, min(log2Ceil(nRows/TageBanks), h))) 376 else 377 Set[FoldedHistoryInfo]() 378 }.reduce(_++_).toSet ++ 379 ITTageTableInfos.map{ case (nRows, h, t) => 380 if (h > 0) 381 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 382 else 383 Set[FoldedHistoryInfo]() 384 }.reduce(_++_) ++ 385 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 386 ).toList 387 388 389 390 val CacheLineSize = coreParams.CacheLineSize 391 val CacheLineHalfWord = CacheLineSize / 16 392 val ExtHistoryLength = HistoryLength + 64 393 val IBufSize = coreParams.IBufSize 394 val DecodeWidth = coreParams.DecodeWidth 395 val RenameWidth = coreParams.RenameWidth 396 val CommitWidth = coreParams.CommitWidth 397 val MaxUopSize = coreParams.MaxUopSize 398 val FtqSize = coreParams.FtqSize 399 val IssQueSize = coreParams.IssQueSize 400 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 401 val IntLogicRegs = coreParams.IntLogicRegs 402 val FpLogicRegs = coreParams.FpLogicRegs 403 val VecLogicRegs = coreParams.VecLogicRegs 404 val NRPhyRegs = coreParams.NRPhyRegs 405 val PhyRegIdxWidth = log2Up(NRPhyRegs) 406 val IntPhyRegs = coreParams.IntPhyRegs 407 val VfPhyRegs = coreParams.VfPhyRegs 408 val IntPregIdxWidth = log2Up(IntPhyRegs) 409 val VfPregIdxWidth = log2Up(VfPhyRegs) 410 val RobSize = coreParams.RobSize 411 val RabSize = coreParams.RabSize 412 val IntRefCounterWidth = log2Ceil(RobSize) 413 val LoadQueueSize = coreParams.LoadQueueSize 414 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 415 val StoreQueueSize = coreParams.StoreQueueSize 416 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 417 val VlsQueueSize = coreParams.VlsQueueSize 418 val dpParams = coreParams.dpParams 419 val exuParameters = coreParams.exuParameters 420 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 421 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 422 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 423 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 424 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 425 val LoadPipelineWidth = coreParams.LoadPipelineWidth 426 val StorePipelineWidth = coreParams.StorePipelineWidth 427 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 428 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 429 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 430 val StoreBufferSize = coreParams.StoreBufferSize 431 val StoreBufferThreshold = coreParams.StoreBufferThreshold 432 val EnsbufferWidth = coreParams.EnsbufferWidth 433 val UncacheBufferSize = coreParams.UncacheBufferSize 434 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 435 val EnableFastForward = coreParams.EnableFastForward 436 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 437 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 438 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 439 val EnableDCacheWPU = coreParams.EnableDCacheWPU 440 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 441 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 442 val asidLen = coreParams.MMUAsidLen 443 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 444 val refillBothTlb = coreParams.refillBothTlb 445 val itlbParams = coreParams.itlbParameters 446 val ldtlbParams = coreParams.ldtlbParameters 447 val sttlbParams = coreParams.sttlbParameters 448 val pftlbParams = coreParams.pftlbParameters 449 val btlbParams = coreParams.btlbParameters 450 val l2tlbParams = coreParams.l2tlbParameters 451 val NumPerfCounters = coreParams.NumPerfCounters 452 453 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 454 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 455 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 456 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 457 458 val instBytes = if (HasCExtension) 2 else 4 459 val instOffsetBits = log2Ceil(instBytes) 460 461 val icacheParameters = coreParams.icacheParameters 462 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 463 464 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 465 // for constrained LR/SC loop 466 val LRSCCycles = 64 467 // for lr storm 468 val LRSCBackOff = 8 469 470 // cache hierarchy configurations 471 val l1BusDataWidth = 256 472 473 // load violation predict 474 val ResetTimeMax2Pow = 20 //1078576 475 val ResetTimeMin2Pow = 10 //1024 476 // wait table parameters 477 val WaitTableSize = 1024 478 val MemPredPCWidth = log2Up(WaitTableSize) 479 val LWTUse2BitCounter = true 480 // store set parameters 481 val SSITSize = WaitTableSize 482 val LFSTSize = 32 483 val SSIDWidth = log2Up(LFSTSize) 484 val LFSTWidth = 4 485 val StoreSetEnable = true // LWT will be disabled if SS is enabled 486 487 val loadExuConfigs = coreParams.loadExuConfigs 488 val storeExuConfigs = coreParams.storeExuConfigs 489 490 val intExuConfigs = coreParams.intExuConfigs 491 492 val fpExuConfigs = coreParams.fpExuConfigs 493 494 val exuConfigs = coreParams.exuConfigs 495 496 val PCntIncrStep: Int = 6 497 val numPCntHc: Int = 25 498 val numPCntPtw: Int = 19 499 500 val numCSRPCntFrontend = 8 501 val numCSRPCntCtrl = 8 502 val numCSRPCntLsu = 8 503 val numCSRPCntHc = 5 504} 505