xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 4c3daa52135920044eef80ed2dd1ed55d596264f) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.dispatch.DispatchParameters
24import xiangshan.cache.DCacheParameters
25import xiangshan.cache.prefetch._
26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB}
27import xiangshan.frontend.icache.ICacheParameters
28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
29import freechips.rocketchip.diplomacy.AddressSet
30import system.SoCParamsKey
31import huancun._
32import huancun.debug._
33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams}
34
35import scala.math.min
36
37case object XSTileKey extends Field[Seq[XSCoreParameters]]
38
39case object XSCoreParamsKey extends Field[XSCoreParameters]
40
41case class XSCoreParameters
42(
43  HasPrefetch: Boolean = false,
44  HartId: Int = 0,
45  XLEN: Int = 64,
46  VLEN: Int = 128,
47  HasMExtension: Boolean = true,
48  HasCExtension: Boolean = true,
49  HasDiv: Boolean = true,
50  HasICache: Boolean = true,
51  HasDCache: Boolean = true,
52  AddrBits: Int = 64,
53  VAddrBits: Int = 39,
54  HasFPU: Boolean = true,
55  HasVPU: Boolean = true,
56  HasCustomCSRCacheOp: Boolean = true,
57  FetchWidth: Int = 8,
58  AsidLength: Int = 16,
59  EnableBPU: Boolean = true,
60  EnableBPD: Boolean = true,
61  EnableRAS: Boolean = true,
62  EnableLB: Boolean = false,
63  EnableLoop: Boolean = true,
64  EnableSC: Boolean = true,
65  EnbaleTlbDebug: Boolean = false,
66  EnableJal: Boolean = false,
67  EnableFauFTB: Boolean = true,
68  UbtbGHRLength: Int = 4,
69  // HistoryLength: Int = 512,
70  EnableGHistDiff: Boolean = true,
71  UbtbSize: Int = 256,
72  FtbSize: Int = 2048,
73  RasSize: Int = 32,
74  CacheLineSize: Int = 512,
75  FtbWays: Int = 4,
76  TageTableInfos: Seq[Tuple3[Int,Int,Int]] =
77  //       Sets  Hist   Tag
78    // Seq(( 2048,    2,    8),
79    //     ( 2048,    9,    8),
80    //     ( 2048,   13,    8),
81    //     ( 2048,   20,    8),
82    //     ( 2048,   26,    8),
83    //     ( 2048,   44,    8),
84    //     ( 2048,   73,    8),
85    //     ( 2048,  256,    8)),
86    Seq(( 4096,    8,    8),
87        ( 4096,   13,    8),
88        ( 4096,   32,    8),
89        ( 4096,  119,    8)),
90  ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] =
91  //      Sets  Hist   Tag
92    Seq(( 256,    4,    9),
93        ( 256,    8,    9),
94        ( 512,   13,    9),
95        ( 512,   16,    9),
96        ( 512,   32,    9)),
97  SCNRows: Int = 512,
98  SCNTables: Int = 4,
99  SCCtrBits: Int = 6,
100  SCHistLens: Seq[Int] = Seq(0, 4, 10, 16),
101  numBr: Int = 2,
102  branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] =
103    ((resp_in: BranchPredictionResp, p: Parameters) => {
104      val ftb = Module(new FTB()(p))
105      val ubtb =Module(new FauFTB()(p))
106      // val bim = Module(new BIM()(p))
107      val tage = Module(new Tage_SC()(p))
108      val ras = Module(new RAS()(p))
109      val ittage = Module(new ITTage()(p))
110      val preds = Seq(ubtb, tage, ftb, ittage, ras)
111      preds.map(_.io := DontCare)
112
113      // ubtb.io.resp_in(0)  := resp_in
114      // bim.io.resp_in(0)   := ubtb.io.resp
115      // btb.io.resp_in(0)   := bim.io.resp
116      // tage.io.resp_in(0)  := btb.io.resp
117      // loop.io.resp_in(0)  := tage.io.resp
118      ubtb.io.in.bits.resp_in(0) := resp_in
119      tage.io.in.bits.resp_in(0) := ubtb.io.out
120      ftb.io.in.bits.resp_in(0)  := tage.io.out
121      ittage.io.in.bits.resp_in(0)  := ftb.io.out
122      ras.io.in.bits.resp_in(0) := ittage.io.out
123
124      (preds, ras.io.out)
125    }),
126  IBufSize: Int = 48,
127  DecodeWidth: Int = 6,
128  RenameWidth: Int = 6,
129  CommitWidth: Int = 6,
130  FtqSize: Int = 64,
131  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
132  IssQueSize: Int = 16,
133  NRPhyRegs: Int = 192,
134  IntPhyRegs: Int = 192,
135  VfPhyRegs: Int = 192,
136  LoadQueueSize: Int = 80,
137  LoadQueueNWriteBanks: Int = 8,
138  StoreQueueSize: Int = 64,
139  StoreQueueNWriteBanks: Int = 8,
140  VlsQueueSize: Int = 8,
141  RobSize: Int = 256,
142  dpParams: DispatchParameters = DispatchParameters(
143    IntDqSize = 16,
144    FpDqSize = 16,
145    LsDqSize = 16,
146    IntDqDeqWidth = 4,
147    FpDqDeqWidth = 4,
148    LsDqDeqWidth = 4
149  ),
150  exuParameters: ExuParameters = ExuParameters(
151    JmpCnt = 1,
152    AluCnt = 4,
153    MulCnt = 0,
154    MduCnt = 2,
155    FmacCnt = 4,
156    FmiscCnt = 2,
157    FmiscDivSqrtCnt = 0,
158    LduCnt = 2,
159    StuCnt = 2
160  ),
161  prefetcher: Option[PrefetcherParams] = Some(SMSParams()),
162  LoadPipelineWidth: Int = 2,
163  StorePipelineWidth: Int = 2,
164  VecMemSrcInWidth: Int = 2,
165  VecMemInstWbWidth: Int = 1,
166  VecMemDispatchWidth: Int = 1,
167  StoreBufferSize: Int = 16,
168  StoreBufferThreshold: Int = 7,
169  EnsbufferWidth: Int = 2,
170  UncacheBufferSize: Int = 4,
171  EnableLoadToLoadForward: Boolean = true,
172  EnableFastForward: Boolean = false,
173  EnableLdVioCheckAfterReset: Boolean = true,
174  EnableSoftPrefetchAfterReset: Boolean = true,
175  EnableCacheErrorAfterReset: Boolean = true,
176  EnableDCacheWPU: Boolean = false,
177  EnableAccurateLoadError: Boolean = true,
178  EnableUncacheWriteOutstanding: Boolean = false,
179  MMUAsidLen: Int = 16, // max is 16, 0 is not supported now
180  ReSelectLen: Int = 6, // load replay queue replay select counter len
181  itlbParameters: TLBParameters = TLBParameters(
182    name = "itlb",
183    fetchi = true,
184    useDmode = false,
185    normalNWays = 32,
186    normalReplacer = Some("plru"),
187    superNWays = 4,
188    superReplacer = Some("plru")
189  ),
190  ldtlbParameters: TLBParameters = TLBParameters(
191    name = "ldtlb",
192    normalNSets = 64,
193    normalNWays = 1,
194    normalAssociative = "sa",
195    normalReplacer = Some("setplru"),
196    superNWays = 16,
197    normalAsVictim = true,
198    outReplace = false,
199    partialStaticPMP = true,
200    outsideRecvFlush = true,
201    saveLevel = true
202  ),
203  sttlbParameters: TLBParameters = TLBParameters(
204    name = "sttlb",
205    normalNSets = 64,
206    normalNWays = 1,
207    normalAssociative = "sa",
208    normalReplacer = Some("setplru"),
209    superNWays = 16,
210    normalAsVictim = true,
211    outReplace = false,
212    partialStaticPMP = true,
213    outsideRecvFlush = true,
214    saveLevel = true
215  ),
216  refillBothTlb: Boolean = false,
217  btlbParameters: TLBParameters = TLBParameters(
218    name = "btlb",
219    normalNSets = 1,
220    normalNWays = 64,
221    superNWays = 4,
222  ),
223  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
224  NumPerfCounters: Int = 16,
225  icacheParameters: ICacheParameters = ICacheParameters(
226    tagECC = Some("parity"),
227    dataECC = Some("parity"),
228    replacer = Some("setplru"),
229    nMissEntries = 2,
230    nProbeEntries = 2,
231    nPrefetchEntries = 2,
232    hasPrefetch = true,
233  ),
234  dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
235    tagECC = Some("secded"),
236    dataECC = Some("secded"),
237    replacer = Some("setplru"),
238    nMissEntries = 16,
239    nProbeEntries = 8,
240    nReleaseEntries = 18
241  )),
242  L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
243    name = "l2",
244    level = 2,
245    ways = 8,
246    sets = 1024, // default 512KB L2
247    prefetch = Some(huancun.prefetch.PrefetchReceiverParams())
248  )),
249  L2NBanks: Int = 1,
250  usePTWRepeater: Boolean = false,
251  softTLB: Boolean = false, // dpi-c l1tlb debug only
252  softPTW: Boolean = false, // dpi-c l2tlb debug only
253  softPTWDelay: Int = 1
254){
255  val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength
256  val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now
257
258  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
259  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
260
261  val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
262    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg)
263
264  val fpExuConfigs =
265    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
266      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
267
268  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
269}
270
271case object DebugOptionsKey extends Field[DebugOptions]
272
273case class DebugOptions
274(
275  FPGAPlatform: Boolean = false,
276  EnableDifftest: Boolean = false,
277  AlwaysBasicDiff: Boolean = true,
278  EnableDebug: Boolean = false,
279  EnablePerfDebug: Boolean = true,
280  UseDRAMSim: Boolean = false,
281  EnableTopDown: Boolean = false
282)
283
284trait HasXSParameter {
285
286  implicit val p: Parameters
287
288  val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits
289
290  val coreParams = p(XSCoreParamsKey)
291  val env = p(DebugOptionsKey)
292
293  val XLEN = coreParams.XLEN
294  val VLEN = coreParams.VLEN
295  val minFLen = 32
296  val fLen = 64
297  def xLen = XLEN
298
299  val HasMExtension = coreParams.HasMExtension
300  val HasCExtension = coreParams.HasCExtension
301  val HasDiv = coreParams.HasDiv
302  val HasIcache = coreParams.HasICache
303  val HasDcache = coreParams.HasDCache
304  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
305  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
306  val AsidLength = coreParams.AsidLength
307  val ReSelectLen = coreParams.ReSelectLen
308  val AddrBytes = AddrBits / 8 // unused
309  val DataBits = XLEN
310  val DataBytes = DataBits / 8
311  val HasFPU = coreParams.HasFPU
312  val HasVPU = coreParams.HasVPU
313  val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp
314  val FetchWidth = coreParams.FetchWidth
315  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
316  val EnableBPU = coreParams.EnableBPU
317  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
318  val EnableRAS = coreParams.EnableRAS
319  val EnableLB = coreParams.EnableLB
320  val EnableLoop = coreParams.EnableLoop
321  val EnableSC = coreParams.EnableSC
322  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
323  val HistoryLength = coreParams.HistoryLength
324  val EnableGHistDiff = coreParams.EnableGHistDiff
325  val UbtbGHRLength = coreParams.UbtbGHRLength
326  val UbtbSize = coreParams.UbtbSize
327  val EnableFauFTB = coreParams.EnableFauFTB
328  val FtbSize = coreParams.FtbSize
329  val FtbWays = coreParams.FtbWays
330  val RasSize = coreParams.RasSize
331
332  def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = {
333    coreParams.branchPredictor(resp_in, p)
334  }
335  val numBr = coreParams.numBr
336  val TageTableInfos = coreParams.TageTableInfos
337  val TageBanks = coreParams.numBr
338  val SCNRows = coreParams.SCNRows
339  val SCCtrBits = coreParams.SCCtrBits
340  val SCHistLens = coreParams.SCHistLens
341  val SCNTables = coreParams.SCNTables
342
343  val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map {
344    case ((n, cb), h) => (n, cb, h)
345  }
346  val ITTageTableInfos = coreParams.ITTageTableInfos
347  type FoldedHistoryInfo = Tuple2[Int, Int]
348  val foldedGHistInfos =
349    (TageTableInfos.map{ case (nRows, h, t) =>
350      if (h > 0)
351        Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1)))
352      else
353        Set[FoldedHistoryInfo]()
354    }.reduce(_++_).toSet ++
355    SCTableInfos.map{ case (nRows, _, h) =>
356      if (h > 0)
357        Set((h, min(log2Ceil(nRows/TageBanks), h)))
358      else
359        Set[FoldedHistoryInfo]()
360    }.reduce(_++_).toSet ++
361    ITTageTableInfos.map{ case (nRows, h, t) =>
362      if (h > 0)
363        Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1)))
364      else
365        Set[FoldedHistoryInfo]()
366    }.reduce(_++_) ++
367      Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize)))
368    ).toList
369
370
371
372  val CacheLineSize = coreParams.CacheLineSize
373  val CacheLineHalfWord = CacheLineSize / 16
374  val ExtHistoryLength = HistoryLength + 64
375  val IBufSize = coreParams.IBufSize
376  val DecodeWidth = coreParams.DecodeWidth
377  val RenameWidth = coreParams.RenameWidth
378  val CommitWidth = coreParams.CommitWidth
379  val FtqSize = coreParams.FtqSize
380  val IssQueSize = coreParams.IssQueSize
381  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
382  val NRPhyRegs = coreParams.NRPhyRegs
383  val PhyRegIdxWidth = log2Up(NRPhyRegs)
384  val IntPhyRegs = coreParams.IntPhyRegs
385  val VfPhyRegs = coreParams.VfPhyRegs
386  val IntPregIdxWidth = log2Up(IntPhyRegs)
387  val VfPregIdxWidth = log2Up(VfPhyRegs)
388  val RobSize = coreParams.RobSize
389  val IntRefCounterWidth = log2Ceil(RobSize)
390  val LoadQueueSize = coreParams.LoadQueueSize
391  val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks
392  val StoreQueueSize = coreParams.StoreQueueSize
393  val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks
394  val VlsQueueSize = coreParams.VlsQueueSize
395  val dpParams = coreParams.dpParams
396  val exuParameters = coreParams.exuParameters
397  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
398  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
399  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
400  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
401  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
402  val LoadPipelineWidth = coreParams.LoadPipelineWidth
403  val StorePipelineWidth = coreParams.StorePipelineWidth
404  val VecMemSrcInWidth = coreParams.VecMemSrcInWidth
405  val VecMemInstWbWidth = coreParams.VecMemInstWbWidth
406  val VecMemDispatchWidth = coreParams.VecMemDispatchWidth
407  val StoreBufferSize = coreParams.StoreBufferSize
408  val StoreBufferThreshold = coreParams.StoreBufferThreshold
409  val EnsbufferWidth = coreParams.EnsbufferWidth
410  val UncacheBufferSize = coreParams.UncacheBufferSize
411  val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward
412  val EnableFastForward = coreParams.EnableFastForward
413  val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset
414  val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset
415  val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset
416  val EnableDCacheWPU = coreParams.EnableDCacheWPU
417  val EnableAccurateLoadError = coreParams.EnableAccurateLoadError
418  val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding
419  val asidLen = coreParams.MMUAsidLen
420  val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
421  val refillBothTlb = coreParams.refillBothTlb
422  val itlbParams = coreParams.itlbParameters
423  val ldtlbParams = coreParams.ldtlbParameters
424  val sttlbParams = coreParams.sttlbParameters
425  val btlbParams = coreParams.btlbParameters
426  val l2tlbParams = coreParams.l2tlbParameters
427  val NumPerfCounters = coreParams.NumPerfCounters
428
429  val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 +
430              (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 +  + (exuParameters.FmiscCnt+1)/2 +
431              (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 +
432              (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2
433
434  val instBytes = if (HasCExtension) 2 else 4
435  val instOffsetBits = log2Ceil(instBytes)
436
437  val icacheParameters = coreParams.icacheParameters
438  val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters())
439
440  // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles
441  // for constrained LR/SC loop
442  val LRSCCycles = 64
443  // for lr storm
444  val LRSCBackOff = 8
445
446  // cache hierarchy configurations
447  val l1BusDataWidth = 256
448
449  // load violation predict
450  val ResetTimeMax2Pow = 20 //1078576
451  val ResetTimeMin2Pow = 10 //1024
452  // wait table parameters
453  val WaitTableSize = 1024
454  val MemPredPCWidth = log2Up(WaitTableSize)
455  val LWTUse2BitCounter = true
456  // store set parameters
457  val SSITSize = WaitTableSize
458  val LFSTSize = 32
459  val SSIDWidth = log2Up(LFSTSize)
460  val LFSTWidth = 4
461  val StoreSetEnable = true // LWT will be disabled if SS is enabled
462
463  val loadExuConfigs = coreParams.loadExuConfigs
464  val storeExuConfigs = coreParams.storeExuConfigs
465
466  val intExuConfigs = coreParams.intExuConfigs
467
468  val fpExuConfigs = coreParams.fpExuConfigs
469
470  val exuConfigs = coreParams.exuConfigs
471
472  val PCntIncrStep: Int = 6
473  val numPCntHc: Int = 25
474  val numPCntPtw: Int = 19
475
476  val numCSRPCntFrontend = 8
477  val numCSRPCntCtrl     = 8
478  val numCSRPCntLsu      = 8
479  val numCSRPCntHc       = 5
480}
481