1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 41case class XSCoreParameters 42( 43 HasPrefetch: Boolean = false, 44 HartId: Int = 0, 45 XLEN: Int = 64, 46 VLEN: Int = 128, 47 HasMExtension: Boolean = true, 48 HasCExtension: Boolean = true, 49 HasDiv: Boolean = true, 50 HasICache: Boolean = true, 51 HasDCache: Boolean = true, 52 AddrBits: Int = 64, 53 VAddrBits: Int = 39, 54 HasFPU: Boolean = true, 55 HasVPU: Boolean = true, 56 HasCustomCSRCacheOp: Boolean = true, 57 FetchWidth: Int = 8, 58 AsidLength: Int = 16, 59 EnableBPU: Boolean = true, 60 EnableBPD: Boolean = true, 61 EnableRAS: Boolean = true, 62 EnableLB: Boolean = false, 63 EnableLoop: Boolean = true, 64 EnableSC: Boolean = true, 65 EnbaleTlbDebug: Boolean = false, 66 EnableJal: Boolean = false, 67 EnableFauFTB: Boolean = true, 68 UbtbGHRLength: Int = 4, 69 // HistoryLength: Int = 512, 70 EnableGHistDiff: Boolean = true, 71 UbtbSize: Int = 256, 72 FtbSize: Int = 2048, 73 RasSize: Int = 32, 74 CacheLineSize: Int = 512, 75 FtbWays: Int = 4, 76 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 77 // Sets Hist Tag 78 // Seq(( 2048, 2, 8), 79 // ( 2048, 9, 8), 80 // ( 2048, 13, 8), 81 // ( 2048, 20, 8), 82 // ( 2048, 26, 8), 83 // ( 2048, 44, 8), 84 // ( 2048, 73, 8), 85 // ( 2048, 256, 8)), 86 Seq(( 4096, 8, 8), 87 ( 4096, 13, 8), 88 ( 4096, 32, 8), 89 ( 4096, 119, 8)), 90 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 Seq(( 256, 4, 9), 93 ( 256, 8, 9), 94 ( 512, 13, 9), 95 ( 512, 16, 9), 96 ( 512, 32, 9)), 97 SCNRows: Int = 512, 98 SCNTables: Int = 4, 99 SCCtrBits: Int = 6, 100 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 101 numBr: Int = 2, 102 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 103 ((resp_in: BranchPredictionResp, p: Parameters) => { 104 val ftb = Module(new FTB()(p)) 105 val ubtb =Module(new FauFTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 val preds = Seq(ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 ubtb.io.in.bits.resp_in(0) := resp_in 119 tage.io.in.bits.resp_in(0) := ubtb.io.out 120 ftb.io.in.bits.resp_in(0) := tage.io.out 121 ittage.io.in.bits.resp_in(0) := ftb.io.out 122 ras.io.in.bits.resp_in(0) := ittage.io.out 123 124 (preds, ras.io.out) 125 }), 126 IBufSize: Int = 48, 127 DecodeWidth: Int = 6, 128 RenameWidth: Int = 6, 129 CommitWidth: Int = 6, 130 FtqSize: Int = 64, 131 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 132 IssQueSize: Int = 16, 133 NRPhyRegs: Int = 192, 134 IntPhyRegs: Int = 192, 135 VfPhyRegs: Int = 192, 136 LoadQueueSize: Int = 80, 137 LoadQueueNWriteBanks: Int = 8, 138 StoreQueueSize: Int = 64, 139 StoreQueueNWriteBanks: Int = 8, 140 VlsQueueSize: Int = 8, 141 RobSize: Int = 256, 142 dpParams: DispatchParameters = DispatchParameters( 143 IntDqSize = 16, 144 FpDqSize = 16, 145 LsDqSize = 16, 146 IntDqDeqWidth = 4, 147 FpDqDeqWidth = 4, 148 LsDqDeqWidth = 4 149 ), 150 exuParameters: ExuParameters = ExuParameters( 151 JmpCnt = 1, 152 AluCnt = 4, 153 MulCnt = 0, 154 MduCnt = 2, 155 FmacCnt = 4, 156 FmiscCnt = 2, 157 FmiscDivSqrtCnt = 0, 158 LduCnt = 2, 159 StuCnt = 2 160 ), 161 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 162 LoadPipelineWidth: Int = 2, 163 StorePipelineWidth: Int = 2, 164 VecMemSrcInWidth: Int = 2, 165 VecMemInstWbWidth: Int = 1, 166 VecMemDispatchWidth: Int = 1, 167 StoreBufferSize: Int = 16, 168 StoreBufferThreshold: Int = 7, 169 EnsbufferWidth: Int = 2, 170 UncacheBufferSize: Int = 4, 171 EnableLoadToLoadForward: Boolean = true, 172 EnableFastForward: Boolean = false, 173 EnableLdVioCheckAfterReset: Boolean = true, 174 EnableSoftPrefetchAfterReset: Boolean = true, 175 EnableCacheErrorAfterReset: Boolean = true, 176 EnableDCacheWPU: Boolean = false, 177 EnableAccurateLoadError: Boolean = true, 178 EnableUncacheWriteOutstanding: Boolean = false, 179 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 180 ReSelectLen: Int = 6, // load replay queue replay select counter len 181 itlbParameters: TLBParameters = TLBParameters( 182 name = "itlb", 183 fetchi = true, 184 useDmode = false, 185 normalNWays = 32, 186 normalReplacer = Some("plru"), 187 superNWays = 4, 188 superReplacer = Some("plru") 189 ), 190 ldtlbParameters: TLBParameters = TLBParameters( 191 name = "ldtlb", 192 normalNSets = 64, 193 normalNWays = 1, 194 normalAssociative = "sa", 195 normalReplacer = Some("setplru"), 196 superNWays = 16, 197 normalAsVictim = true, 198 outReplace = false, 199 partialStaticPMP = true, 200 outsideRecvFlush = true, 201 saveLevel = true 202 ), 203 sttlbParameters: TLBParameters = TLBParameters( 204 name = "sttlb", 205 normalNSets = 64, 206 normalNWays = 1, 207 normalAssociative = "sa", 208 normalReplacer = Some("setplru"), 209 superNWays = 16, 210 normalAsVictim = true, 211 outReplace = false, 212 partialStaticPMP = true, 213 outsideRecvFlush = true, 214 saveLevel = true 215 ), 216 pftlbParameters: TLBParameters = TLBParameters( 217 name = "pftlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 refillBothTlb: Boolean = false, 230 btlbParameters: TLBParameters = TLBParameters( 231 name = "btlb", 232 normalNSets = 1, 233 normalNWays = 64, 234 superNWays = 4, 235 ), 236 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 237 NumPerfCounters: Int = 16, 238 icacheParameters: ICacheParameters = ICacheParameters( 239 tagECC = Some("parity"), 240 dataECC = Some("parity"), 241 replacer = Some("setplru"), 242 nMissEntries = 2, 243 nProbeEntries = 2, 244 nPrefetchEntries = 2, 245 hasPrefetch = true, 246 ), 247 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 248 tagECC = Some("secded"), 249 dataECC = Some("secded"), 250 replacer = Some("setplru"), 251 nMissEntries = 16, 252 nProbeEntries = 8, 253 nReleaseEntries = 18 254 )), 255 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 256 name = "l2", 257 level = 2, 258 ways = 8, 259 sets = 1024, // default 512KB L2 260 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 261 )), 262 L2NBanks: Int = 1, 263 usePTWRepeater: Boolean = false, 264 softTLB: Boolean = false, // dpi-c l1tlb debug only 265 softPTW: Boolean = false, // dpi-c l2tlb debug only 266 softPTWDelay: Int = 1 267){ 268 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 269 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 270 271 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 272 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 273 274 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 275 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 276 277 val fpExuConfigs = 278 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 279 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 280 281 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 282} 283 284case object DebugOptionsKey extends Field[DebugOptions] 285 286case class DebugOptions 287( 288 FPGAPlatform: Boolean = false, 289 EnableDifftest: Boolean = false, 290 AlwaysBasicDiff: Boolean = true, 291 EnableDebug: Boolean = false, 292 EnablePerfDebug: Boolean = true, 293 UseDRAMSim: Boolean = false, 294 EnableTopDown: Boolean = false 295) 296 297trait HasXSParameter { 298 299 implicit val p: Parameters 300 301 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 302 303 val coreParams = p(XSCoreParamsKey) 304 val env = p(DebugOptionsKey) 305 306 val XLEN = coreParams.XLEN 307 val VLEN = coreParams.VLEN 308 val minFLen = 32 309 val fLen = 64 310 def xLen = XLEN 311 312 val HasMExtension = coreParams.HasMExtension 313 val HasCExtension = coreParams.HasCExtension 314 val HasDiv = coreParams.HasDiv 315 val HasIcache = coreParams.HasICache 316 val HasDcache = coreParams.HasDCache 317 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 318 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 319 val AsidLength = coreParams.AsidLength 320 val ReSelectLen = coreParams.ReSelectLen 321 val AddrBytes = AddrBits / 8 // unused 322 val DataBits = XLEN 323 val DataBytes = DataBits / 8 324 val HasFPU = coreParams.HasFPU 325 val HasVPU = coreParams.HasVPU 326 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 327 val FetchWidth = coreParams.FetchWidth 328 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 329 val EnableBPU = coreParams.EnableBPU 330 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 331 val EnableRAS = coreParams.EnableRAS 332 val EnableLB = coreParams.EnableLB 333 val EnableLoop = coreParams.EnableLoop 334 val EnableSC = coreParams.EnableSC 335 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 336 val HistoryLength = coreParams.HistoryLength 337 val EnableGHistDiff = coreParams.EnableGHistDiff 338 val UbtbGHRLength = coreParams.UbtbGHRLength 339 val UbtbSize = coreParams.UbtbSize 340 val EnableFauFTB = coreParams.EnableFauFTB 341 val FtbSize = coreParams.FtbSize 342 val FtbWays = coreParams.FtbWays 343 val RasSize = coreParams.RasSize 344 345 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 346 coreParams.branchPredictor(resp_in, p) 347 } 348 val numBr = coreParams.numBr 349 val TageTableInfos = coreParams.TageTableInfos 350 val TageBanks = coreParams.numBr 351 val SCNRows = coreParams.SCNRows 352 val SCCtrBits = coreParams.SCCtrBits 353 val SCHistLens = coreParams.SCHistLens 354 val SCNTables = coreParams.SCNTables 355 356 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 357 case ((n, cb), h) => (n, cb, h) 358 } 359 val ITTageTableInfos = coreParams.ITTageTableInfos 360 type FoldedHistoryInfo = Tuple2[Int, Int] 361 val foldedGHistInfos = 362 (TageTableInfos.map{ case (nRows, h, t) => 363 if (h > 0) 364 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 365 else 366 Set[FoldedHistoryInfo]() 367 }.reduce(_++_).toSet ++ 368 SCTableInfos.map{ case (nRows, _, h) => 369 if (h > 0) 370 Set((h, min(log2Ceil(nRows/TageBanks), h))) 371 else 372 Set[FoldedHistoryInfo]() 373 }.reduce(_++_).toSet ++ 374 ITTageTableInfos.map{ case (nRows, h, t) => 375 if (h > 0) 376 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 377 else 378 Set[FoldedHistoryInfo]() 379 }.reduce(_++_) ++ 380 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 381 ).toList 382 383 384 385 val CacheLineSize = coreParams.CacheLineSize 386 val CacheLineHalfWord = CacheLineSize / 16 387 val ExtHistoryLength = HistoryLength + 64 388 val IBufSize = coreParams.IBufSize 389 val DecodeWidth = coreParams.DecodeWidth 390 val RenameWidth = coreParams.RenameWidth 391 val CommitWidth = coreParams.CommitWidth 392 val FtqSize = coreParams.FtqSize 393 val IssQueSize = coreParams.IssQueSize 394 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 395 val NRPhyRegs = coreParams.NRPhyRegs 396 val PhyRegIdxWidth = log2Up(NRPhyRegs) 397 val IntPhyRegs = coreParams.IntPhyRegs 398 val VfPhyRegs = coreParams.VfPhyRegs 399 val IntPregIdxWidth = log2Up(IntPhyRegs) 400 val VfPregIdxWidth = log2Up(VfPhyRegs) 401 val RobSize = coreParams.RobSize 402 val IntRefCounterWidth = log2Ceil(RobSize) 403 val LoadQueueSize = coreParams.LoadQueueSize 404 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 405 val StoreQueueSize = coreParams.StoreQueueSize 406 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 407 val VlsQueueSize = coreParams.VlsQueueSize 408 val dpParams = coreParams.dpParams 409 val exuParameters = coreParams.exuParameters 410 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 411 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 412 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 413 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 414 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 415 val LoadPipelineWidth = coreParams.LoadPipelineWidth 416 val StorePipelineWidth = coreParams.StorePipelineWidth 417 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 418 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 419 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 420 val StoreBufferSize = coreParams.StoreBufferSize 421 val StoreBufferThreshold = coreParams.StoreBufferThreshold 422 val EnsbufferWidth = coreParams.EnsbufferWidth 423 val UncacheBufferSize = coreParams.UncacheBufferSize 424 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 425 val EnableFastForward = coreParams.EnableFastForward 426 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 427 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 428 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 429 val EnableDCacheWPU = coreParams.EnableDCacheWPU 430 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 431 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 432 val asidLen = coreParams.MMUAsidLen 433 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 434 val refillBothTlb = coreParams.refillBothTlb 435 val itlbParams = coreParams.itlbParameters 436 val ldtlbParams = coreParams.ldtlbParameters 437 val sttlbParams = coreParams.sttlbParameters 438 val pftlbParams = coreParams.pftlbParameters 439 val btlbParams = coreParams.btlbParameters 440 val l2tlbParams = coreParams.l2tlbParameters 441 val NumPerfCounters = coreParams.NumPerfCounters 442 443 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 444 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 445 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 446 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 447 448 val instBytes = if (HasCExtension) 2 else 4 449 val instOffsetBits = log2Ceil(instBytes) 450 451 val icacheParameters = coreParams.icacheParameters 452 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 453 454 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 455 // for constrained LR/SC loop 456 val LRSCCycles = 64 457 // for lr storm 458 val LRSCBackOff = 8 459 460 // cache hierarchy configurations 461 val l1BusDataWidth = 256 462 463 // load violation predict 464 val ResetTimeMax2Pow = 20 //1078576 465 val ResetTimeMin2Pow = 10 //1024 466 // wait table parameters 467 val WaitTableSize = 1024 468 val MemPredPCWidth = log2Up(WaitTableSize) 469 val LWTUse2BitCounter = true 470 // store set parameters 471 val SSITSize = WaitTableSize 472 val LFSTSize = 32 473 val SSIDWidth = log2Up(LFSTSize) 474 val LFSTWidth = 4 475 val StoreSetEnable = true // LWT will be disabled if SS is enabled 476 477 val loadExuConfigs = coreParams.loadExuConfigs 478 val storeExuConfigs = coreParams.storeExuConfigs 479 480 val intExuConfigs = coreParams.intExuConfigs 481 482 val fpExuConfigs = coreParams.fpExuConfigs 483 484 val exuConfigs = coreParams.exuConfigs 485 486 val PCntIncrStep: Int = 6 487 val numPCntHc: Int = 25 488 val numPCntPtw: Int = 19 489 490 val numCSRPCntFrontend = 8 491 val numCSRPCntCtrl = 8 492 val numCSRPCntLsu = 8 493 val numCSRPCntHc = 5 494} 495