1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 41case class XSCoreParameters 42( 43 HasPrefetch: Boolean = false, 44 HartId: Int = 0, 45 XLEN: Int = 64, 46 VLEN: Int = 128, 47 HasMExtension: Boolean = true, 48 HasCExtension: Boolean = true, 49 HasDiv: Boolean = true, 50 HasICache: Boolean = true, 51 HasDCache: Boolean = true, 52 AddrBits: Int = 64, 53 VAddrBits: Int = 39, 54 HasFPU: Boolean = true, 55 HasVPU: Boolean = true, 56 HasCustomCSRCacheOp: Boolean = true, 57 FetchWidth: Int = 8, 58 AsidLength: Int = 16, 59 EnableBPU: Boolean = true, 60 EnableBPD: Boolean = true, 61 EnableRAS: Boolean = true, 62 EnableLB: Boolean = false, 63 EnableLoop: Boolean = true, 64 EnableSC: Boolean = true, 65 EnbaleTlbDebug: Boolean = false, 66 EnableJal: Boolean = false, 67 EnableFauFTB: Boolean = true, 68 UbtbGHRLength: Int = 4, 69 // HistoryLength: Int = 512, 70 EnableGHistDiff: Boolean = true, 71 UbtbSize: Int = 256, 72 FtbSize: Int = 2048, 73 RasSize: Int = 32, 74 CacheLineSize: Int = 512, 75 FtbWays: Int = 4, 76 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 77 // Sets Hist Tag 78 // Seq(( 2048, 2, 8), 79 // ( 2048, 9, 8), 80 // ( 2048, 13, 8), 81 // ( 2048, 20, 8), 82 // ( 2048, 26, 8), 83 // ( 2048, 44, 8), 84 // ( 2048, 73, 8), 85 // ( 2048, 256, 8)), 86 Seq(( 4096, 8, 8), 87 ( 4096, 13, 8), 88 ( 4096, 32, 8), 89 ( 4096, 119, 8)), 90 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 Seq(( 256, 4, 9), 93 ( 256, 8, 9), 94 ( 512, 13, 9), 95 ( 512, 16, 9), 96 ( 512, 32, 9)), 97 SCNRows: Int = 512, 98 SCNTables: Int = 4, 99 SCCtrBits: Int = 6, 100 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 101 numBr: Int = 2, 102 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 103 ((resp_in: BranchPredictionResp, p: Parameters) => { 104 val ftb = Module(new FTB()(p)) 105 val ubtb =Module(new FauFTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 val preds = Seq(ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 ubtb.io.in.bits.resp_in(0) := resp_in 119 tage.io.in.bits.resp_in(0) := ubtb.io.out 120 ftb.io.in.bits.resp_in(0) := tage.io.out 121 ittage.io.in.bits.resp_in(0) := ftb.io.out 122 ras.io.in.bits.resp_in(0) := ittage.io.out 123 124 (preds, ras.io.out) 125 }), 126 IBufSize: Int = 48, 127 DecodeWidth: Int = 6, 128 RenameWidth: Int = 6, 129 CommitWidth: Int = 6, 130 FtqSize: Int = 64, 131 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 132 IssQueSize: Int = 16, 133 IntLogicRegs: Int = 33, 134 FpLogicRegs: Int = 34, 135 VecLogicRegs: Int = 34, 136 NRPhyRegs: Int = 192, 137 IntPhyRegs: Int = 192, 138 VfPhyRegs: Int = 192, 139 LoadQueueSize: Int = 80, 140 LoadQueueNWriteBanks: Int = 8, 141 StoreQueueSize: Int = 64, 142 StoreQueueNWriteBanks: Int = 8, 143 VlsQueueSize: Int = 8, 144 RobSize: Int = 256, 145 dpParams: DispatchParameters = DispatchParameters( 146 IntDqSize = 16, 147 FpDqSize = 16, 148 LsDqSize = 16, 149 IntDqDeqWidth = 4, 150 FpDqDeqWidth = 4, 151 LsDqDeqWidth = 4 152 ), 153 exuParameters: ExuParameters = ExuParameters( 154 JmpCnt = 1, 155 AluCnt = 4, 156 MulCnt = 0, 157 MduCnt = 2, 158 FmacCnt = 4, 159 FmiscCnt = 2, 160 FmiscDivSqrtCnt = 0, 161 LduCnt = 2, 162 StuCnt = 2 163 ), 164 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 165 LoadPipelineWidth: Int = 2, 166 StorePipelineWidth: Int = 2, 167 VecMemSrcInWidth: Int = 2, 168 VecMemInstWbWidth: Int = 1, 169 VecMemDispatchWidth: Int = 1, 170 StoreBufferSize: Int = 16, 171 StoreBufferThreshold: Int = 7, 172 EnsbufferWidth: Int = 2, 173 UncacheBufferSize: Int = 4, 174 EnableLoadToLoadForward: Boolean = true, 175 EnableFastForward: Boolean = false, 176 EnableLdVioCheckAfterReset: Boolean = true, 177 EnableSoftPrefetchAfterReset: Boolean = true, 178 EnableCacheErrorAfterReset: Boolean = true, 179 EnableDCacheWPU: Boolean = false, 180 EnableAccurateLoadError: Boolean = true, 181 EnableUncacheWriteOutstanding: Boolean = false, 182 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 183 ReSelectLen: Int = 6, // load replay queue replay select counter len 184 itlbParameters: TLBParameters = TLBParameters( 185 name = "itlb", 186 fetchi = true, 187 useDmode = false, 188 normalNWays = 32, 189 normalReplacer = Some("plru"), 190 superNWays = 4, 191 superReplacer = Some("plru") 192 ), 193 ldtlbParameters: TLBParameters = TLBParameters( 194 name = "ldtlb", 195 normalNSets = 64, 196 normalNWays = 1, 197 normalAssociative = "sa", 198 normalReplacer = Some("setplru"), 199 superNWays = 16, 200 normalAsVictim = true, 201 outReplace = false, 202 partialStaticPMP = true, 203 outsideRecvFlush = true, 204 saveLevel = true 205 ), 206 sttlbParameters: TLBParameters = TLBParameters( 207 name = "sttlb", 208 normalNSets = 64, 209 normalNWays = 1, 210 normalAssociative = "sa", 211 normalReplacer = Some("setplru"), 212 superNWays = 16, 213 normalAsVictim = true, 214 outReplace = false, 215 partialStaticPMP = true, 216 outsideRecvFlush = true, 217 saveLevel = true 218 ), 219 pftlbParameters: TLBParameters = TLBParameters( 220 name = "pftlb", 221 normalNSets = 64, 222 normalNWays = 1, 223 normalAssociative = "sa", 224 normalReplacer = Some("setplru"), 225 superNWays = 16, 226 normalAsVictim = true, 227 outReplace = false, 228 partialStaticPMP = true, 229 outsideRecvFlush = true, 230 saveLevel = true 231 ), 232 refillBothTlb: Boolean = false, 233 btlbParameters: TLBParameters = TLBParameters( 234 name = "btlb", 235 normalNSets = 1, 236 normalNWays = 64, 237 superNWays = 4, 238 ), 239 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 240 NumPerfCounters: Int = 16, 241 icacheParameters: ICacheParameters = ICacheParameters( 242 tagECC = Some("parity"), 243 dataECC = Some("parity"), 244 replacer = Some("setplru"), 245 nMissEntries = 2, 246 nProbeEntries = 2, 247 nPrefetchEntries = 2, 248 hasPrefetch = true, 249 ), 250 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 251 tagECC = Some("secded"), 252 dataECC = Some("secded"), 253 replacer = Some("setplru"), 254 nMissEntries = 16, 255 nProbeEntries = 8, 256 nReleaseEntries = 18 257 )), 258 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 259 name = "l2", 260 level = 2, 261 ways = 8, 262 sets = 1024, // default 512KB L2 263 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 264 )), 265 L2NBanks: Int = 1, 266 usePTWRepeater: Boolean = false, 267 softTLB: Boolean = false, // dpi-c l1tlb debug only 268 softPTW: Boolean = false, // dpi-c l2tlb debug only 269 softPTWDelay: Int = 1 270){ 271 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 272 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 273 274 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 275 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 276 277 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 278 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 279 280 val fpExuConfigs = 281 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 282 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 283 284 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 285} 286 287case object DebugOptionsKey extends Field[DebugOptions] 288 289case class DebugOptions 290( 291 FPGAPlatform: Boolean = false, 292 EnableDifftest: Boolean = false, 293 AlwaysBasicDiff: Boolean = true, 294 EnableDebug: Boolean = false, 295 EnablePerfDebug: Boolean = true, 296 UseDRAMSim: Boolean = false, 297 EnableTopDown: Boolean = false 298) 299 300trait HasXSParameter { 301 302 implicit val p: Parameters 303 304 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 305 306 val coreParams = p(XSCoreParamsKey) 307 val env = p(DebugOptionsKey) 308 309 val XLEN = coreParams.XLEN 310 val VLEN = coreParams.VLEN 311 val minFLen = 32 312 val fLen = 64 313 def xLen = XLEN 314 315 val HasMExtension = coreParams.HasMExtension 316 val HasCExtension = coreParams.HasCExtension 317 val HasDiv = coreParams.HasDiv 318 val HasIcache = coreParams.HasICache 319 val HasDcache = coreParams.HasDCache 320 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 321 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 322 val AsidLength = coreParams.AsidLength 323 val ReSelectLen = coreParams.ReSelectLen 324 val AddrBytes = AddrBits / 8 // unused 325 val DataBits = XLEN 326 val DataBytes = DataBits / 8 327 val HasFPU = coreParams.HasFPU 328 val HasVPU = coreParams.HasVPU 329 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 330 val FetchWidth = coreParams.FetchWidth 331 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 332 val EnableBPU = coreParams.EnableBPU 333 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 334 val EnableRAS = coreParams.EnableRAS 335 val EnableLB = coreParams.EnableLB 336 val EnableLoop = coreParams.EnableLoop 337 val EnableSC = coreParams.EnableSC 338 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 339 val HistoryLength = coreParams.HistoryLength 340 val EnableGHistDiff = coreParams.EnableGHistDiff 341 val UbtbGHRLength = coreParams.UbtbGHRLength 342 val UbtbSize = coreParams.UbtbSize 343 val EnableFauFTB = coreParams.EnableFauFTB 344 val FtbSize = coreParams.FtbSize 345 val FtbWays = coreParams.FtbWays 346 val RasSize = coreParams.RasSize 347 348 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 349 coreParams.branchPredictor(resp_in, p) 350 } 351 val numBr = coreParams.numBr 352 val TageTableInfos = coreParams.TageTableInfos 353 val TageBanks = coreParams.numBr 354 val SCNRows = coreParams.SCNRows 355 val SCCtrBits = coreParams.SCCtrBits 356 val SCHistLens = coreParams.SCHistLens 357 val SCNTables = coreParams.SCNTables 358 359 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 360 case ((n, cb), h) => (n, cb, h) 361 } 362 val ITTageTableInfos = coreParams.ITTageTableInfos 363 type FoldedHistoryInfo = Tuple2[Int, Int] 364 val foldedGHistInfos = 365 (TageTableInfos.map{ case (nRows, h, t) => 366 if (h > 0) 367 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 368 else 369 Set[FoldedHistoryInfo]() 370 }.reduce(_++_).toSet ++ 371 SCTableInfos.map{ case (nRows, _, h) => 372 if (h > 0) 373 Set((h, min(log2Ceil(nRows/TageBanks), h))) 374 else 375 Set[FoldedHistoryInfo]() 376 }.reduce(_++_).toSet ++ 377 ITTageTableInfos.map{ case (nRows, h, t) => 378 if (h > 0) 379 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 380 else 381 Set[FoldedHistoryInfo]() 382 }.reduce(_++_) ++ 383 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 384 ).toList 385 386 387 388 val CacheLineSize = coreParams.CacheLineSize 389 val CacheLineHalfWord = CacheLineSize / 16 390 val ExtHistoryLength = HistoryLength + 64 391 val IBufSize = coreParams.IBufSize 392 val DecodeWidth = coreParams.DecodeWidth 393 val RenameWidth = coreParams.RenameWidth 394 val CommitWidth = coreParams.CommitWidth 395 val FtqSize = coreParams.FtqSize 396 val IssQueSize = coreParams.IssQueSize 397 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 398 val IntLogicRegs = coreParams.IntLogicRegs 399 val FpLogicRegs = coreParams.FpLogicRegs 400 val VecLogicRegs = coreParams.VecLogicRegs 401 val NRPhyRegs = coreParams.NRPhyRegs 402 val PhyRegIdxWidth = log2Up(NRPhyRegs) 403 val IntPhyRegs = coreParams.IntPhyRegs 404 val VfPhyRegs = coreParams.VfPhyRegs 405 val IntPregIdxWidth = log2Up(IntPhyRegs) 406 val VfPregIdxWidth = log2Up(VfPhyRegs) 407 val RobSize = coreParams.RobSize 408 val IntRefCounterWidth = log2Ceil(RobSize) 409 val LoadQueueSize = coreParams.LoadQueueSize 410 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 411 val StoreQueueSize = coreParams.StoreQueueSize 412 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 413 val VlsQueueSize = coreParams.VlsQueueSize 414 val dpParams = coreParams.dpParams 415 val exuParameters = coreParams.exuParameters 416 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 417 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 418 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 419 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 420 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 421 val LoadPipelineWidth = coreParams.LoadPipelineWidth 422 val StorePipelineWidth = coreParams.StorePipelineWidth 423 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 424 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 425 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 426 val StoreBufferSize = coreParams.StoreBufferSize 427 val StoreBufferThreshold = coreParams.StoreBufferThreshold 428 val EnsbufferWidth = coreParams.EnsbufferWidth 429 val UncacheBufferSize = coreParams.UncacheBufferSize 430 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 431 val EnableFastForward = coreParams.EnableFastForward 432 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 433 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 434 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 435 val EnableDCacheWPU = coreParams.EnableDCacheWPU 436 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 437 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 438 val asidLen = coreParams.MMUAsidLen 439 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 440 val refillBothTlb = coreParams.refillBothTlb 441 val itlbParams = coreParams.itlbParameters 442 val ldtlbParams = coreParams.ldtlbParameters 443 val sttlbParams = coreParams.sttlbParameters 444 val pftlbParams = coreParams.pftlbParameters 445 val btlbParams = coreParams.btlbParameters 446 val l2tlbParams = coreParams.l2tlbParameters 447 val NumPerfCounters = coreParams.NumPerfCounters 448 449 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 450 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 451 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 452 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 453 454 val instBytes = if (HasCExtension) 2 else 4 455 val instOffsetBits = log2Ceil(instBytes) 456 457 val icacheParameters = coreParams.icacheParameters 458 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 459 460 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 461 // for constrained LR/SC loop 462 val LRSCCycles = 64 463 // for lr storm 464 val LRSCBackOff = 8 465 466 // cache hierarchy configurations 467 val l1BusDataWidth = 256 468 469 // load violation predict 470 val ResetTimeMax2Pow = 20 //1078576 471 val ResetTimeMin2Pow = 10 //1024 472 // wait table parameters 473 val WaitTableSize = 1024 474 val MemPredPCWidth = log2Up(WaitTableSize) 475 val LWTUse2BitCounter = true 476 // store set parameters 477 val SSITSize = WaitTableSize 478 val LFSTSize = 32 479 val SSIDWidth = log2Up(LFSTSize) 480 val LFSTWidth = 4 481 val StoreSetEnable = true // LWT will be disabled if SS is enabled 482 483 val loadExuConfigs = coreParams.loadExuConfigs 484 val storeExuConfigs = coreParams.storeExuConfigs 485 486 val intExuConfigs = coreParams.intExuConfigs 487 488 val fpExuConfigs = coreParams.fpExuConfigs 489 490 val exuConfigs = coreParams.exuConfigs 491 492 val PCntIncrStep: Int = 6 493 val numPCntHc: Int = 25 494 val numPCntPtw: Int = 19 495 496 val numCSRPCntFrontend = 8 497 val numCSRPCntCtrl = 8 498 val numCSRPCntLsu = 8 499 val numCSRPCntHc = 5 500} 501