History log of /XiangShan/src/main/scala/xiangshan/Parameters.scala (Results 226 – 250 of 451)
Revision Date Author Comments
# c61abc0c 06-Aug-2023 Xuan Hu <[email protected]>

merge master into new-backend

Todo: fix error


# fd6a6c99 04-Aug-2023 Xuan Hu <[email protected]>

params,backend: merge piped fu, use less exu


# 39c59369 03-Aug-2023 Xuan Hu <[email protected]>

params,backend: refactor RegFile parameters


# acb0b98e 21-Jul-2023 Xuan Hu <[email protected]>

params,backend: add more alu and modify the regfile r/w params


# 344c8465 03-Aug-2023 xiaofeibao-xjtu <[email protected]>

parms: add vector exeunit


# 04665835 28-Jul-2023 Maxpicca-Li <[email protected]>

DCacheWPU: update the latest version (#2095)

Co-authored-by: bugGenerator <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: Haoyuan Feng <fenghaoyuan19@mails

DCacheWPU: update the latest version (#2095)

Co-authored-by: bugGenerator <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: Haoyuan Feng <[email protected]>

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# cdbff57c 24-Jul-2023 Haoyuan Feng <[email protected]>

Memblock: Add load/store 128 bits datapath (#2180)

* Memblock: Add load/store 128 bits datapath

---------

Co-authored-by: lulu0521 <[email protected]>

* Memblock: fix bug of raw addr ma

Memblock: Add load/store 128 bits datapath (#2180)

* Memblock: Add load/store 128 bits datapath

---------

Co-authored-by: lulu0521 <[email protected]>

* Memblock: fix bug of raw addr match

* Memblock, LoadUnit: Fix Vector RAW paddr match

---------

Co-authored-by: lulu0521 <[email protected]>

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# 75841254 23-Jul-2023 xiaofeibao-xjtu <[email protected]>

exu: vfdivsqrt support all instructions


# cfbf6f34 14-Jul-2023 Xuan Hu <[email protected]>

params,backend: modify reg rw params and add more wake up bundles


# c0be7f33 19-Jul-2023 Xuan Hu <[email protected]>

backend,iq: split wake up bundles, add cancel bundle

* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
*

backend,iq: split wake up bundles, add cancel bundle

* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
* Add srcTimer in StatusArray to record the cycles src has been waked up
* Add dataSources in StatusArray to record the source of src data (reg, forward, bypass or none)
* Remove useless ready field in StatusArray

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# bf35baad 19-Jul-2023 Xuan Hu <[email protected]>

backend: add iq wake up


# fa7f2c26 20-Jul-2023 Tang Haojin <[email protected]>

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* sn

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* snapshot: add rename snapshot switch

* CtrlBlock: add snapshotGen API

* snapshot: optimize timing

* snapshot: put snapshot logic in a module

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# 14a67055 12-Jul-2023 sfencevma <[email protected]>

ldu, stu: Refactoring the code for ldu/stu (#2171)

* add new ldu and stu

* add fast replay kill at s1

* fix pointer chasing cancel

* pick flushpipe_rvc

* merge flushpipe_rvc

* fix s3_

ldu, stu: Refactoring the code for ldu/stu (#2171)

* add new ldu and stu

* add fast replay kill at s1

* fix pointer chasing cancel

* pick flushpipe_rvc

* merge flushpipe_rvc

* fix s3_cache_rep and s3_feedbacked

* fix fast replay condition

---------

Co-authored-by: Lyn <[email protected]>

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# a74b2cda 06-Jul-2023 Ziyue Zhang <[email protected]>

vector: add the connection for reduction


# cd1420fb 06-Jul-2023 xiaofeibao-xjtu <[email protected]>

exu: vfadd lmul1 test pass


# cde70b38 05-Jul-2023 zhanglyGit <[email protected]>

Backend: dispatch2Iq support Alu + AluMul IQ


# ad22c988 03-Jul-2023 Ziyue Zhang <[email protected]>

vector: add the connection for permutation


# efdf5c1c 03-Jul-2023 xiaofeibao-xjtu <[email protected]>

exu:add vfalu vfma vfdivsqrt


# 44cbc983 15-Jun-2023 sfencevma <[email protected]>

LQ: fix replay logic for 3ld2st (#2136)

Co-authored-by: Lyn <[email protected]>


# 08017d75 10-Jun-2023 Xuan Hu <[email protected]>

exu: add name in ExeUnitParams


# 2372d0fb 12-Jun-2023 fdy <[email protected]>

Parameters: modify some ExeUnitParams


# 3fd20bec 17-May-2023 czw <[email protected]>

func(WbBusyArbiter):add WbBusyArbiter


# 0162f462 24-Apr-2023 czw <[email protected]>

type(FpWb): delete FpWB & rename VecWB to VfWB


# fa35b2ce 10-Jun-2023 zhanglyGit <[email protected]>

fix: fix Preg Num in DefaultConfig


# 62129679 06-Jun-2023 wakafa <[email protected]>

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump hua

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump huancun & utility

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