1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.backend.datapath.WakeUpConfig 46import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 47 48import scala.math.min 49 50case object XSTileKey extends Field[Seq[XSCoreParameters]] 51 52case object XSCoreParamsKey extends Field[XSCoreParameters] 53 54case class XSCoreParameters 55( 56 HasPrefetch: Boolean = false, 57 HartId: Int = 0, 58 XLEN: Int = 64, 59 VLEN: Int = 128, 60 ELEN: Int = 64, 61 HasMExtension: Boolean = true, 62 HasCExtension: Boolean = true, 63 HasDiv: Boolean = true, 64 HasICache: Boolean = true, 65 HasDCache: Boolean = true, 66 AddrBits: Int = 64, 67 VAddrBits: Int = 39, 68 HasFPU: Boolean = true, 69 HasVPU: Boolean = true, 70 HasCustomCSRCacheOp: Boolean = true, 71 FetchWidth: Int = 8, 72 AsidLength: Int = 16, 73 EnableBPU: Boolean = true, 74 EnableBPD: Boolean = true, 75 EnableRAS: Boolean = true, 76 EnableLB: Boolean = false, 77 EnableLoop: Boolean = true, 78 EnableSC: Boolean = true, 79 EnbaleTlbDebug: Boolean = false, 80 EnableJal: Boolean = false, 81 EnableFauFTB: Boolean = true, 82 UbtbGHRLength: Int = 4, 83 // HistoryLength: Int = 512, 84 EnableGHistDiff: Boolean = true, 85 EnableCommitGHistDiff: Boolean = true, 86 UbtbSize: Int = 256, 87 FtbSize: Int = 2048, 88 RasSize: Int = 32, 89 CacheLineSize: Int = 512, 90 FtbWays: Int = 4, 91 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 92 // Sets Hist Tag 93 // Seq(( 2048, 2, 8), 94 // ( 2048, 9, 8), 95 // ( 2048, 13, 8), 96 // ( 2048, 20, 8), 97 // ( 2048, 26, 8), 98 // ( 2048, 44, 8), 99 // ( 2048, 73, 8), 100 // ( 2048, 256, 8)), 101 Seq(( 4096, 8, 8), 102 ( 4096, 13, 8), 103 ( 4096, 32, 8), 104 ( 4096, 119, 8)), 105 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 256, 4, 9), 108 ( 256, 8, 9), 109 ( 512, 13, 9), 110 ( 512, 16, 9), 111 ( 512, 32, 9)), 112 SCNRows: Int = 512, 113 SCNTables: Int = 4, 114 SCCtrBits: Int = 6, 115 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 116 numBr: Int = 2, 117 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 118 ((resp_in: BranchPredictionResp, p: Parameters) => { 119 val ftb = Module(new FTB()(p)) 120 val ubtb =Module(new FauFTB()(p)) 121 // val bim = Module(new BIM()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(ubtb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 // ubtb.io.resp_in(0) := resp_in 129 // bim.io.resp_in(0) := ubtb.io.resp 130 // btb.io.resp_in(0) := bim.io.resp 131 // tage.io.resp_in(0) := btb.io.resp 132 // loop.io.resp_in(0) := tage.io.resp 133 ubtb.io.in.bits.resp_in(0) := resp_in 134 tage.io.in.bits.resp_in(0) := ubtb.io.out 135 ftb.io.in.bits.resp_in(0) := tage.io.out 136 ittage.io.in.bits.resp_in(0) := ftb.io.out 137 ras.io.in.bits.resp_in(0) := ittage.io.out 138 139 (preds, ras.io.out) 140 }), 141 IBufSize: Int = 48, 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 6, 145 MaxUopSize: Int = 65, 146 FtqSize: Int = 64, 147 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 148 IntLogicRegs: Int = 32, 149 FpLogicRegs: Int = 33, 150 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 151 VCONFIG_IDX: Int = 32, 152 NRPhyRegs: Int = 192, 153 IntPhyRegs: Int = 192, 154 VfPhyRegs: Int = 192, 155 VirtualLoadQueueSize: Int = 80, 156 LoadQueueRARSize: Int = 80, 157 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 158 RollbackGroupSize: Int = 8, 159 LoadQueueReplaySize: Int = 80, 160 LoadUncacheBufferSize: Int = 20, 161 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 162 StoreQueueSize: Int = 64, 163 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 164 StoreQueueForwardWithMask: Boolean = true, 165 VlsQueueSize: Int = 8, 166 RobSize: Int = 256, 167 RabSize: Int = 256, 168 dpParams: DispatchParameters = DispatchParameters( 169 IntDqSize = 16, 170 FpDqSize = 16, 171 LsDqSize = 16, 172 IntDqDeqWidth = 6, 173 FpDqDeqWidth = 6, 174 LsDqDeqWidth = 6, 175 ), 176 intPreg: PregParams = IntPregParams( 177 numEntries = 256, 178 numRead = 14, 179 numWrite = 8, 180 ), 181 vfPreg: VfPregParams = VfPregParams( 182 numEntries = 256, 183 numRead = 14, 184 numWrite = 8, 185 ), 186 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 187 LoadPipelineWidth: Int = 2, 188 StorePipelineWidth: Int = 2, 189 VecMemSrcInWidth: Int = 2, 190 VecMemInstWbWidth: Int = 1, 191 VecMemDispatchWidth: Int = 1, 192 StoreBufferSize: Int = 16, 193 StoreBufferThreshold: Int = 7, 194 EnsbufferWidth: Int = 2, 195 UncacheBufferSize: Int = 4, 196 EnableLoadToLoadForward: Boolean = true, 197 EnableFastForward: Boolean = false, 198 EnableLdVioCheckAfterReset: Boolean = true, 199 EnableSoftPrefetchAfterReset: Boolean = true, 200 EnableCacheErrorAfterReset: Boolean = true, 201 EnableDCacheWPU: Boolean = false, 202 EnableAccurateLoadError: Boolean = true, 203 EnableUncacheWriteOutstanding: Boolean = false, 204 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 205 ReSelectLen: Int = 7, // load replay queue replay select counter len 206 itlbParameters: TLBParameters = TLBParameters( 207 name = "itlb", 208 fetchi = true, 209 useDmode = false, 210 normalNWays = 32, 211 normalReplacer = Some("plru"), 212 superNWays = 4, 213 superReplacer = Some("plru") 214 ), 215 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 217 ldtlbParameters: TLBParameters = TLBParameters( 218 name = "ldtlb", 219 normalNSets = 64, 220 normalNWays = 1, 221 normalAssociative = "sa", 222 normalReplacer = Some("setplru"), 223 superNWays = 16, 224 normalAsVictim = true, 225 outReplace = false, 226 partialStaticPMP = true, 227 outsideRecvFlush = true, 228 saveLevel = true 229 ), 230 sttlbParameters: TLBParameters = TLBParameters( 231 name = "sttlb", 232 normalNSets = 64, 233 normalNWays = 1, 234 normalAssociative = "sa", 235 normalReplacer = Some("setplru"), 236 superNWays = 16, 237 normalAsVictim = true, 238 outReplace = false, 239 partialStaticPMP = true, 240 outsideRecvFlush = true, 241 saveLevel = true 242 ), 243 pftlbParameters: TLBParameters = TLBParameters( 244 name = "pftlb", 245 normalNSets = 64, 246 normalNWays = 1, 247 normalAssociative = "sa", 248 normalReplacer = Some("setplru"), 249 superNWays = 16, 250 normalAsVictim = true, 251 outReplace = false, 252 partialStaticPMP = true, 253 outsideRecvFlush = true, 254 saveLevel = true 255 ), 256 refillBothTlb: Boolean = false, 257 btlbParameters: TLBParameters = TLBParameters( 258 name = "btlb", 259 normalNSets = 1, 260 normalNWays = 64, 261 superNWays = 4, 262 ), 263 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 264 NumPerfCounters: Int = 16, 265 icacheParameters: ICacheParameters = ICacheParameters( 266 tagECC = Some("parity"), 267 dataECC = Some("parity"), 268 replacer = Some("setplru"), 269 nMissEntries = 2, 270 nProbeEntries = 2, 271 nPrefetchEntries = 12, 272 nPrefBufferEntries = 64, 273 hasPrefetch = true, 274 ), 275 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 276 tagECC = Some("secded"), 277 dataECC = Some("secded"), 278 replacer = Some("setplru"), 279 nMissEntries = 16, 280 nProbeEntries = 8, 281 nReleaseEntries = 18 282 )), 283 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 284 name = "l2", 285 ways = 8, 286 sets = 1024, // default 512KB L2 287 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 288 )), 289 L2NBanks: Int = 1, 290 usePTWRepeater: Boolean = false, 291 softTLB: Boolean = false, // dpi-c l1tlb debug only 292 softPTW: Boolean = false, // dpi-c l2tlb debug only 293 softPTWDelay: Int = 1 294){ 295 def vlWidth = log2Up(VLEN) + 1 296 297 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 298 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 299 300 def intSchdParams = { 301 implicit val schdType: SchedulerType = IntScheduler() 302 val pregBits = intPreg.addrWidth 303 val numRfRead = intPreg.numRead 304 val numRfWrite = intPreg.numWrite 305 SchdBlockParams(Seq( 306 IssueBlockParams(Seq( 307 ExeUnitParams("IEX0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 308 ExeUnitParams("IEX1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 309 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 310 IssueBlockParams(Seq( 311 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 312 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 313 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 314 IssueBlockParams(Seq( 315 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 2)), Seq(IntRD(7, 2)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams("IMISC1", Seq(I2fCfg, VSetRiWvfCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1)))), 319 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 320 IssueBlockParams(Seq( 321 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 322 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 323 ), 324 numPregs = intPreg.numEntries, 325 numRfReadWrite = Some((numRfRead, numRfWrite)), 326 numDeqOutside = 0, 327 schdType = schdType, 328 rfDataWidth = intPreg.dataCfg.dataWidth, 329 numUopIn = dpParams.IntDqDeqWidth, 330 ) 331 } 332 def vfSchdParams = { 333 implicit val schdType: SchedulerType = VfScheduler() 334 val pregBits = vfPreg.addrWidth 335 val numRfRead = vfPreg.numRead 336 val numRfWrite = vfPreg.numWrite 337 SchdBlockParams(Seq( 338 IssueBlockParams(Seq( 339 ExeUnitParams("VEX0", Seq(VialuCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 340 ExeUnitParams("VEX1", Seq(VimacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 341 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 342 IssueBlockParams(Seq( 343 ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))), 344 ExeUnitParams("FEX1", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(VfRD(6, 0)))), 345 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 346 IssueBlockParams(Seq( 347 ExeUnitParams("FEX2", Seq(FDivSqrtCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(11, 0)), Seq(VfRD(12, 0)))), 348 ExeUnitParams("FEX3", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)))), 349 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 350 IssueBlockParams(Seq( 351 ExeUnitParams("VEX2", Seq(VppuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 352 ExeUnitParams("VEX3", Seq(VipuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 353 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 354 IssueBlockParams(Seq( 355 ExeUnitParams("VEX2", Seq(VfaluCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 356 ExeUnitParams("VEX3", Seq(VfmaCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 357 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 358 IssueBlockParams(Seq( 359 ExeUnitParams("VEX4", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 360 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 361 ), 362 numPregs = vfPreg.numEntries, 363 numRfReadWrite = Some((numRfRead, numRfWrite)), 364 numDeqOutside = 0, 365 schdType = schdType, 366 rfDataWidth = vfPreg.dataCfg.dataWidth, 367 numUopIn = dpParams.FpDqDeqWidth, 368 ) 369 } 370 def memSchdParams = { 371 implicit val schdType: SchedulerType = MemScheduler() 372 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 373 val rfDataWidth = 64 374 375 SchdBlockParams(Seq( 376 IssueBlockParams(Seq( 377 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 378 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 379 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 380 IssueBlockParams(Seq( 381 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))), 382 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))), 383 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 384 IssueBlockParams(Seq( 385 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 386 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(13, Int.MaxValue)))), 387 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 388 IssueBlockParams(Seq( 389 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 390 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 391 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 392 ), 393 numPregs = intPreg.numEntries max vfPreg.numEntries, 394 numRfReadWrite = None, 395 numDeqOutside = 0, 396 schdType = schdType, 397 rfDataWidth = rfDataWidth, 398 numUopIn = dpParams.LsDqDeqWidth, 399 ) 400 } 401 402 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 403 404 def iqWakeUpParams = { 405 Seq( 406 WakeUpConfig("IEX0" -> "IEX0"), 407 WakeUpConfig("IEX0" -> "IEX1"), 408 WakeUpConfig("IEX1" -> "IEX0"), 409 WakeUpConfig("IEX1" -> "IEX1"), 410 WakeUpConfig("IEX0" -> "BJU0"), 411 WakeUpConfig("IEX0" -> "BJU1"), 412 WakeUpConfig("IEX1" -> "BJU0"), 413 WakeUpConfig("IEX1" -> "BJU1"), 414 WakeUpConfig("IEX0" -> "LDU0"), 415 WakeUpConfig("IEX0" -> "LDU1"), 416 WakeUpConfig("IEX1" -> "LDU0"), 417 WakeUpConfig("IEX1" -> "LDU1"), 418 WakeUpConfig("IEX0" -> "STA0"), 419 WakeUpConfig("IEX0" -> "STA1"), 420 WakeUpConfig("IEX1" -> "STA0"), 421 WakeUpConfig("IEX1" -> "STA1"), 422 WakeUpConfig("IMISC1" -> "FEX0"), 423 WakeUpConfig("IMISC1" -> "FEX1"), 424 WakeUpConfig("IMISC1" -> "FEX2"), 425 WakeUpConfig("IMISC1" -> "FEX3"), 426 WakeUpConfig("IMISC1" -> "FEX4"), 427 WakeUpConfig("FEX3" -> "FEX0"), 428 WakeUpConfig("FEX3" -> "FEX1"), 429 WakeUpConfig("FEX3" -> "FEX2"), 430 WakeUpConfig("FEX3" -> "FEX3"), 431 WakeUpConfig("FEX3" -> "IEX0"), 432 WakeUpConfig("FEX3" -> "IEX1"), 433 WakeUpConfig("FEX3" -> "BJU0"), 434 WakeUpConfig("FEX3" -> "BJU1"), 435 ) 436 } 437 438 def backendParams: BackendParams = backend.BackendParams( 439 Map( 440 IntScheduler() -> intSchdParams, 441 VfScheduler() -> vfSchdParams, 442 MemScheduler() -> memSchdParams, 443 ), 444 Seq( 445 intPreg, 446 vfPreg, 447 ), 448 iqWakeUpParams, 449 ) 450} 451 452case object DebugOptionsKey extends Field[DebugOptions] 453 454case class DebugOptions 455( 456 FPGAPlatform: Boolean = false, 457 EnableDifftest: Boolean = false, 458 AlwaysBasicDiff: Boolean = true, 459 EnableDebug: Boolean = false, 460 EnablePerfDebug: Boolean = true, 461 UseDRAMSim: Boolean = false, 462 EnableConstantin: Boolean = false, 463 EnableTopDown: Boolean = false 464) 465 466trait HasXSParameter { 467 468 implicit val p: Parameters 469 470 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 471 472 val coreParams = p(XSCoreParamsKey) 473 val env = p(DebugOptionsKey) 474 475 val XLEN = coreParams.XLEN 476 val VLEN = coreParams.VLEN 477 val ELEN = coreParams.ELEN 478 val minFLen = 32 479 val fLen = 64 480 def xLen = XLEN 481 482 val HasMExtension = coreParams.HasMExtension 483 val HasCExtension = coreParams.HasCExtension 484 val HasDiv = coreParams.HasDiv 485 val HasIcache = coreParams.HasICache 486 val HasDcache = coreParams.HasDCache 487 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 488 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 489 val AsidLength = coreParams.AsidLength 490 val ReSelectLen = coreParams.ReSelectLen 491 val AddrBytes = AddrBits / 8 // unused 492 val DataBits = XLEN 493 val DataBytes = DataBits / 8 494 val HasFPU = coreParams.HasFPU 495 val HasVPU = coreParams.HasVPU 496 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 497 val FetchWidth = coreParams.FetchWidth 498 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 499 val EnableBPU = coreParams.EnableBPU 500 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 501 val EnableRAS = coreParams.EnableRAS 502 val EnableLB = coreParams.EnableLB 503 val EnableLoop = coreParams.EnableLoop 504 val EnableSC = coreParams.EnableSC 505 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 506 val HistoryLength = coreParams.HistoryLength 507 val EnableGHistDiff = coreParams.EnableGHistDiff 508 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 509 val UbtbGHRLength = coreParams.UbtbGHRLength 510 val UbtbSize = coreParams.UbtbSize 511 val EnableFauFTB = coreParams.EnableFauFTB 512 val FtbSize = coreParams.FtbSize 513 val FtbWays = coreParams.FtbWays 514 val RasSize = coreParams.RasSize 515 516 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 517 coreParams.branchPredictor(resp_in, p) 518 } 519 val numBr = coreParams.numBr 520 val TageTableInfos = coreParams.TageTableInfos 521 val TageBanks = coreParams.numBr 522 val SCNRows = coreParams.SCNRows 523 val SCCtrBits = coreParams.SCCtrBits 524 val SCHistLens = coreParams.SCHistLens 525 val SCNTables = coreParams.SCNTables 526 527 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 528 case ((n, cb), h) => (n, cb, h) 529 } 530 val ITTageTableInfos = coreParams.ITTageTableInfos 531 type FoldedHistoryInfo = Tuple2[Int, Int] 532 val foldedGHistInfos = 533 (TageTableInfos.map{ case (nRows, h, t) => 534 if (h > 0) 535 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 536 else 537 Set[FoldedHistoryInfo]() 538 }.reduce(_++_).toSet ++ 539 SCTableInfos.map{ case (nRows, _, h) => 540 if (h > 0) 541 Set((h, min(log2Ceil(nRows/TageBanks), h))) 542 else 543 Set[FoldedHistoryInfo]() 544 }.reduce(_++_).toSet ++ 545 ITTageTableInfos.map{ case (nRows, h, t) => 546 if (h > 0) 547 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 548 else 549 Set[FoldedHistoryInfo]() 550 }.reduce(_++_) ++ 551 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 552 ).toList 553 554 555 556 val CacheLineSize = coreParams.CacheLineSize 557 val CacheLineHalfWord = CacheLineSize / 16 558 val ExtHistoryLength = HistoryLength + 64 559 val IBufSize = coreParams.IBufSize 560 val DecodeWidth = coreParams.DecodeWidth 561 val RenameWidth = coreParams.RenameWidth 562 val CommitWidth = coreParams.CommitWidth 563 val MaxUopSize = coreParams.MaxUopSize 564 val FtqSize = coreParams.FtqSize 565 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 566 val IntLogicRegs = coreParams.IntLogicRegs 567 val FpLogicRegs = coreParams.FpLogicRegs 568 val VecLogicRegs = coreParams.VecLogicRegs 569 val VCONFIG_IDX = coreParams.VCONFIG_IDX 570 val NRPhyRegs = coreParams.NRPhyRegs 571 val PhyRegIdxWidth = log2Up(NRPhyRegs) 572 val IntPhyRegs = coreParams.IntPhyRegs 573 val VfPhyRegs = coreParams.VfPhyRegs 574 val IntPregIdxWidth = log2Up(IntPhyRegs) 575 val VfPregIdxWidth = log2Up(VfPhyRegs) 576 val RobSize = coreParams.RobSize 577 val RabSize = coreParams.RabSize 578 val IntRefCounterWidth = log2Ceil(RobSize) 579 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 580 val LoadQueueRARSize = coreParams.LoadQueueRARSize 581 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 582 val RollbackGroupSize = coreParams.RollbackGroupSize 583 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 584 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 585 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 586 val StoreQueueSize = coreParams.StoreQueueSize 587 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 588 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 589 val VlsQueueSize = coreParams.VlsQueueSize 590 val dpParams = coreParams.dpParams 591 592 def backendParams: BackendParams = coreParams.backendParams 593 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 594 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 595 val LoadPipelineWidth = coreParams.LoadPipelineWidth 596 val StorePipelineWidth = coreParams.StorePipelineWidth 597 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 598 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 599 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 600 val StoreBufferSize = coreParams.StoreBufferSize 601 val StoreBufferThreshold = coreParams.StoreBufferThreshold 602 val EnsbufferWidth = coreParams.EnsbufferWidth 603 val UncacheBufferSize = coreParams.UncacheBufferSize 604 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 605 val EnableFastForward = coreParams.EnableFastForward 606 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 607 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 608 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 609 val EnableDCacheWPU = coreParams.EnableDCacheWPU 610 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 611 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 612 val asidLen = coreParams.MMUAsidLen 613 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 614 val refillBothTlb = coreParams.refillBothTlb 615 val itlbParams = coreParams.itlbParameters 616 val ldtlbParams = coreParams.ldtlbParameters 617 val sttlbParams = coreParams.sttlbParameters 618 val pftlbParams = coreParams.pftlbParameters 619 val btlbParams = coreParams.btlbParameters 620 val l2tlbParams = coreParams.l2tlbParameters 621 val NumPerfCounters = coreParams.NumPerfCounters 622 623 val instBytes = if (HasCExtension) 2 else 4 624 val instOffsetBits = log2Ceil(instBytes) 625 626 val icacheParameters = coreParams.icacheParameters 627 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 628 629 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 630 // for constrained LR/SC loop 631 val LRSCCycles = 64 632 // for lr storm 633 val LRSCBackOff = 8 634 635 // cache hierarchy configurations 636 val l1BusDataWidth = 256 637 638 // load violation predict 639 val ResetTimeMax2Pow = 20 //1078576 640 val ResetTimeMin2Pow = 10 //1024 641 // wait table parameters 642 val WaitTableSize = 1024 643 val MemPredPCWidth = log2Up(WaitTableSize) 644 val LWTUse2BitCounter = true 645 // store set parameters 646 val SSITSize = WaitTableSize 647 val LFSTSize = 32 648 val SSIDWidth = log2Up(LFSTSize) 649 val LFSTWidth = 4 650 val StoreSetEnable = true // LWT will be disabled if SS is enabled 651 val LFSTEnable = false 652 653 val PCntIncrStep: Int = 6 654 val numPCntHc: Int = 25 655 val numPCntPtw: Int = 19 656 657 val numCSRPCntFrontend = 8 658 val numCSRPCntCtrl = 8 659 val numCSRPCntLsu = 8 660 val numCSRPCntHc = 5 661 662 // source stages of cancel signal to issue queues 663 val cancelStages = Seq("IS", "OG0", "OG1") 664} 665