1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 46 47import scala.math.min 48 49case object XSTileKey extends Field[Seq[XSCoreParameters]] 50 51case object XSCoreParamsKey extends Field[XSCoreParameters] 52 53case class XSCoreParameters 54( 55 HasPrefetch: Boolean = false, 56 HartId: Int = 0, 57 XLEN: Int = 64, 58 VLEN: Int = 128, 59 ELEN: Int = 64, 60 HasMExtension: Boolean = true, 61 HasCExtension: Boolean = true, 62 HasDiv: Boolean = true, 63 HasICache: Boolean = true, 64 HasDCache: Boolean = true, 65 AddrBits: Int = 64, 66 VAddrBits: Int = 39, 67 HasFPU: Boolean = true, 68 HasVPU: Boolean = true, 69 HasCustomCSRCacheOp: Boolean = true, 70 FetchWidth: Int = 8, 71 AsidLength: Int = 16, 72 EnableBPU: Boolean = true, 73 EnableBPD: Boolean = true, 74 EnableRAS: Boolean = true, 75 EnableLB: Boolean = false, 76 EnableLoop: Boolean = true, 77 EnableSC: Boolean = true, 78 EnbaleTlbDebug: Boolean = false, 79 EnableJal: Boolean = false, 80 EnableFauFTB: Boolean = true, 81 UbtbGHRLength: Int = 4, 82 // HistoryLength: Int = 512, 83 EnableGHistDiff: Boolean = true, 84 EnableCommitGHistDiff: Boolean = true, 85 UbtbSize: Int = 256, 86 FtbSize: Int = 2048, 87 RasSize: Int = 32, 88 CacheLineSize: Int = 512, 89 FtbWays: Int = 4, 90 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 // Seq(( 2048, 2, 8), 93 // ( 2048, 9, 8), 94 // ( 2048, 13, 8), 95 // ( 2048, 20, 8), 96 // ( 2048, 26, 8), 97 // ( 2048, 44, 8), 98 // ( 2048, 73, 8), 99 // ( 2048, 256, 8)), 100 Seq(( 4096, 8, 8), 101 ( 4096, 13, 8), 102 ( 4096, 32, 8), 103 ( 4096, 119, 8)), 104 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 256, 4, 9), 107 ( 256, 8, 9), 108 ( 512, 13, 9), 109 ( 512, 16, 9), 110 ( 512, 32, 9)), 111 SCNRows: Int = 512, 112 SCNTables: Int = 4, 113 SCCtrBits: Int = 6, 114 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 115 numBr: Int = 2, 116 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 117 ((resp_in: BranchPredictionResp, p: Parameters) => { 118 val ftb = Module(new FTB()(p)) 119 val ubtb =Module(new FauFTB()(p)) 120 // val bim = Module(new BIM()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(ubtb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 // ubtb.io.resp_in(0) := resp_in 128 // bim.io.resp_in(0) := ubtb.io.resp 129 // btb.io.resp_in(0) := bim.io.resp 130 // tage.io.resp_in(0) := btb.io.resp 131 // loop.io.resp_in(0) := tage.io.resp 132 ubtb.io.in.bits.resp_in(0) := resp_in 133 tage.io.in.bits.resp_in(0) := ubtb.io.out 134 ftb.io.in.bits.resp_in(0) := tage.io.out 135 ittage.io.in.bits.resp_in(0) := ftb.io.out 136 ras.io.in.bits.resp_in(0) := ittage.io.out 137 138 (preds, ras.io.out) 139 }), 140 IBufSize: Int = 48, 141 DecodeWidth: Int = 6, 142 RenameWidth: Int = 6, 143 CommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 FtqSize: Int = 64, 146 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 147 IntLogicRegs: Int = 32, 148 FpLogicRegs: Int = 33, 149 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 150 VCONFIG_IDX: Int = 32, 151 NRPhyRegs: Int = 192, 152 IntPhyRegs: Int = 192, 153 VfPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 80, 155 LoadQueueRARSize: Int = 80, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 80, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 256, 166 RabSize: Int = 256, 167 dpParams: DispatchParameters = DispatchParameters( 168 IntDqSize = 16, 169 FpDqSize = 16, 170 LsDqSize = 16, 171 IntDqDeqWidth = 6, 172 FpDqDeqWidth = 6, 173 LsDqDeqWidth = 6, 174 ), 175 intPreg: PregParams = IntPregParams( 176 numEntries = 256, 177 numRead = 14, 178 numWrite = 8, 179 ), 180 vfPreg: VfPregParams = VfPregParams( 181 numEntries = 256, 182 numRead = 14, 183 numWrite = 8, 184 ), 185 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 186 LoadPipelineWidth: Int = 2, 187 StorePipelineWidth: Int = 2, 188 VecMemSrcInWidth: Int = 2, 189 VecMemInstWbWidth: Int = 1, 190 VecMemDispatchWidth: Int = 1, 191 StoreBufferSize: Int = 16, 192 StoreBufferThreshold: Int = 7, 193 EnsbufferWidth: Int = 2, 194 UncacheBufferSize: Int = 4, 195 EnableLoadToLoadForward: Boolean = true, 196 EnableFastForward: Boolean = false, 197 EnableLdVioCheckAfterReset: Boolean = true, 198 EnableSoftPrefetchAfterReset: Boolean = true, 199 EnableCacheErrorAfterReset: Boolean = true, 200 EnableDCacheWPU: Boolean = false, 201 EnableAccurateLoadError: Boolean = true, 202 EnableUncacheWriteOutstanding: Boolean = false, 203 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 204 ReSelectLen: Int = 7, // load replay queue replay select counter len 205 itlbParameters: TLBParameters = TLBParameters( 206 name = "itlb", 207 fetchi = true, 208 useDmode = false, 209 normalNWays = 32, 210 normalReplacer = Some("plru"), 211 superNWays = 4, 212 superReplacer = Some("plru") 213 ), 214 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ldtlbParameters: TLBParameters = TLBParameters( 217 name = "ldtlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 sttlbParameters: TLBParameters = TLBParameters( 230 name = "sttlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 pftlbParameters: TLBParameters = TLBParameters( 243 name = "pftlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 refillBothTlb: Boolean = false, 256 btlbParameters: TLBParameters = TLBParameters( 257 name = "btlb", 258 normalNSets = 1, 259 normalNWays = 64, 260 superNWays = 4, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 64, 272 hasPrefetch = true, 273 ), 274 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 275 tagECC = Some("secded"), 276 dataECC = Some("secded"), 277 replacer = Some("setplru"), 278 nMissEntries = 16, 279 nProbeEntries = 8, 280 nReleaseEntries = 18 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 def vlWidth = log2Up(VLEN) + 1 295 296 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 297 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 298 299 def intSchdParams = { 300 implicit val schdType: SchedulerType = IntScheduler() 301 val pregBits = intPreg.addrWidth 302 val numRfRead = intPreg.numRead 303 val numRfWrite = intPreg.numWrite 304 SchdBlockParams(Seq( 305 IssueBlockParams(Seq( 306 ExeUnitParams("IEX0", Seq(AluCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(2, 2)), Seq(IntRD(3, 2)))), 307 ExeUnitParams("IEX1", Seq(AluCfg), Seq(IntWB(port = 3, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 308 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams("IEX0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 311 ExeUnitParams("IEX1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 312 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 315 ExeUnitParams("IDIV1", Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 319 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 320 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 321 IssueBlockParams(Seq( 322 ExeUnitParams("IMISC0", Seq(I2fCfg, VSetRiWiCfg), Seq(VfWB(port = 3, Int.MaxValue), IntWB(port = 1, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 323 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 324 IssueBlockParams(Seq( 325 ExeUnitParams("IMISC1", Seq(VSetRiWvfCfg), Seq(VfWB(port = 3, Int.MaxValue)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 326 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 327 ), 328 numPregs = intPreg.numEntries, 329 numRfReadWrite = Some((numRfRead, numRfWrite)), 330 numDeqOutside = 0, 331 schdType = schdType, 332 rfDataWidth = intPreg.dataCfg.dataWidth, 333 numUopIn = dpParams.IntDqDeqWidth, 334 ) 335 } 336 def vfSchdParams = { 337 implicit val schdType: SchedulerType = VfScheduler() 338 val pregBits = vfPreg.addrWidth 339 val numRfRead = vfPreg.numRead 340 val numRfWrite = vfPreg.numWrite 341 SchdBlockParams(Seq( 342 IssueBlockParams(Seq( 343 ExeUnitParams("VEX0", Seq(VialuCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 344 ExeUnitParams("VEX1", Seq(VimacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 345 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 346 IssueBlockParams(Seq( 347 ExeUnitParams("VEX2", Seq(VppuCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 348 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 349 IssueBlockParams(Seq( 350 ExeUnitParams("VEX3", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 351 ExeUnitParams("VEX4", Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 0, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 352 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 353 IssueBlockParams(Seq( 354 ExeUnitParams("VEX4", Seq(VfaluCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 355 ExeUnitParams("VEX5", Seq(VfmaCfg) , Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 356 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 357 ), 358 numPregs = vfPreg.numEntries, 359 numRfReadWrite = Some((numRfRead, numRfWrite)), 360 numDeqOutside = 0, 361 schdType = schdType, 362 rfDataWidth = vfPreg.dataCfg.dataWidth, 363 numUopIn = dpParams.FpDqDeqWidth, 364 ) 365 } 366 def memSchdParams = { 367 implicit val schdType: SchedulerType = MemScheduler() 368 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 369 val rfDataWidth = 64 370 371 SchdBlockParams(Seq( 372 IssueBlockParams(Seq( 373 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 374 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 375 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 376 IssueBlockParams(Seq( 377 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 378 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 379 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 380 IssueBlockParams(Seq( 381 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 382 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 383 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 384 IssueBlockParams(Seq( 385 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 386 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 0)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 387 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 388 ), 389 numPregs = intPreg.numEntries max vfPreg.numEntries, 390 numRfReadWrite = None, 391 numDeqOutside = 0, 392 schdType = schdType, 393 rfDataWidth = rfDataWidth, 394 numUopIn = dpParams.LsDqDeqWidth, 395 ) 396 } 397 398 def backendParams: BackendParams = backend.BackendParams(Map( 399 IntScheduler() -> intSchdParams, 400 VfScheduler() -> vfSchdParams, 401 MemScheduler() -> memSchdParams, 402 ), Seq( 403 intPreg, 404 vfPreg, 405 )) 406} 407 408case object DebugOptionsKey extends Field[DebugOptions] 409 410case class DebugOptions 411( 412 FPGAPlatform: Boolean = false, 413 EnableDifftest: Boolean = false, 414 AlwaysBasicDiff: Boolean = true, 415 EnableDebug: Boolean = false, 416 EnablePerfDebug: Boolean = true, 417 UseDRAMSim: Boolean = false, 418 EnableConstantin: Boolean = false, 419 EnableTopDown: Boolean = false 420) 421 422trait HasXSParameter { 423 424 implicit val p: Parameters 425 426 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 427 428 val coreParams = p(XSCoreParamsKey) 429 val env = p(DebugOptionsKey) 430 431 val XLEN = coreParams.XLEN 432 val VLEN = coreParams.VLEN 433 val ELEN = coreParams.ELEN 434 val minFLen = 32 435 val fLen = 64 436 def xLen = XLEN 437 438 val HasMExtension = coreParams.HasMExtension 439 val HasCExtension = coreParams.HasCExtension 440 val HasDiv = coreParams.HasDiv 441 val HasIcache = coreParams.HasICache 442 val HasDcache = coreParams.HasDCache 443 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 444 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 445 val AsidLength = coreParams.AsidLength 446 val ReSelectLen = coreParams.ReSelectLen 447 val AddrBytes = AddrBits / 8 // unused 448 val DataBits = XLEN 449 val DataBytes = DataBits / 8 450 val HasFPU = coreParams.HasFPU 451 val HasVPU = coreParams.HasVPU 452 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 453 val FetchWidth = coreParams.FetchWidth 454 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 455 val EnableBPU = coreParams.EnableBPU 456 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 457 val EnableRAS = coreParams.EnableRAS 458 val EnableLB = coreParams.EnableLB 459 val EnableLoop = coreParams.EnableLoop 460 val EnableSC = coreParams.EnableSC 461 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 462 val HistoryLength = coreParams.HistoryLength 463 val EnableGHistDiff = coreParams.EnableGHistDiff 464 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 465 val UbtbGHRLength = coreParams.UbtbGHRLength 466 val UbtbSize = coreParams.UbtbSize 467 val EnableFauFTB = coreParams.EnableFauFTB 468 val FtbSize = coreParams.FtbSize 469 val FtbWays = coreParams.FtbWays 470 val RasSize = coreParams.RasSize 471 472 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 473 coreParams.branchPredictor(resp_in, p) 474 } 475 val numBr = coreParams.numBr 476 val TageTableInfos = coreParams.TageTableInfos 477 val TageBanks = coreParams.numBr 478 val SCNRows = coreParams.SCNRows 479 val SCCtrBits = coreParams.SCCtrBits 480 val SCHistLens = coreParams.SCHistLens 481 val SCNTables = coreParams.SCNTables 482 483 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 484 case ((n, cb), h) => (n, cb, h) 485 } 486 val ITTageTableInfos = coreParams.ITTageTableInfos 487 type FoldedHistoryInfo = Tuple2[Int, Int] 488 val foldedGHistInfos = 489 (TageTableInfos.map{ case (nRows, h, t) => 490 if (h > 0) 491 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 492 else 493 Set[FoldedHistoryInfo]() 494 }.reduce(_++_).toSet ++ 495 SCTableInfos.map{ case (nRows, _, h) => 496 if (h > 0) 497 Set((h, min(log2Ceil(nRows/TageBanks), h))) 498 else 499 Set[FoldedHistoryInfo]() 500 }.reduce(_++_).toSet ++ 501 ITTageTableInfos.map{ case (nRows, h, t) => 502 if (h > 0) 503 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 504 else 505 Set[FoldedHistoryInfo]() 506 }.reduce(_++_) ++ 507 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 508 ).toList 509 510 511 512 val CacheLineSize = coreParams.CacheLineSize 513 val CacheLineHalfWord = CacheLineSize / 16 514 val ExtHistoryLength = HistoryLength + 64 515 val IBufSize = coreParams.IBufSize 516 val DecodeWidth = coreParams.DecodeWidth 517 val RenameWidth = coreParams.RenameWidth 518 val CommitWidth = coreParams.CommitWidth 519 val MaxUopSize = coreParams.MaxUopSize 520 val FtqSize = coreParams.FtqSize 521 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 522 val IntLogicRegs = coreParams.IntLogicRegs 523 val FpLogicRegs = coreParams.FpLogicRegs 524 val VecLogicRegs = coreParams.VecLogicRegs 525 val VCONFIG_IDX = coreParams.VCONFIG_IDX 526 val NRPhyRegs = coreParams.NRPhyRegs 527 val PhyRegIdxWidth = log2Up(NRPhyRegs) 528 val IntPhyRegs = coreParams.IntPhyRegs 529 val VfPhyRegs = coreParams.VfPhyRegs 530 val IntPregIdxWidth = log2Up(IntPhyRegs) 531 val VfPregIdxWidth = log2Up(VfPhyRegs) 532 val RobSize = coreParams.RobSize 533 val RabSize = coreParams.RabSize 534 val IntRefCounterWidth = log2Ceil(RobSize) 535 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 536 val LoadQueueRARSize = coreParams.LoadQueueRARSize 537 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 538 val RollbackGroupSize = coreParams.RollbackGroupSize 539 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 540 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 541 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 542 val StoreQueueSize = coreParams.StoreQueueSize 543 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 544 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 545 val VlsQueueSize = coreParams.VlsQueueSize 546 val dpParams = coreParams.dpParams 547 548 def backendParams: BackendParams = coreParams.backendParams 549 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 550 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 551 val LoadPipelineWidth = coreParams.LoadPipelineWidth 552 val StorePipelineWidth = coreParams.StorePipelineWidth 553 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 554 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 555 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 556 val StoreBufferSize = coreParams.StoreBufferSize 557 val StoreBufferThreshold = coreParams.StoreBufferThreshold 558 val EnsbufferWidth = coreParams.EnsbufferWidth 559 val UncacheBufferSize = coreParams.UncacheBufferSize 560 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 561 val EnableFastForward = coreParams.EnableFastForward 562 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 563 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 564 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 565 val EnableDCacheWPU = coreParams.EnableDCacheWPU 566 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 567 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 568 val asidLen = coreParams.MMUAsidLen 569 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 570 val refillBothTlb = coreParams.refillBothTlb 571 val itlbParams = coreParams.itlbParameters 572 val ldtlbParams = coreParams.ldtlbParameters 573 val sttlbParams = coreParams.sttlbParameters 574 val pftlbParams = coreParams.pftlbParameters 575 val btlbParams = coreParams.btlbParameters 576 val l2tlbParams = coreParams.l2tlbParameters 577 val NumPerfCounters = coreParams.NumPerfCounters 578 579 val instBytes = if (HasCExtension) 2 else 4 580 val instOffsetBits = log2Ceil(instBytes) 581 582 val icacheParameters = coreParams.icacheParameters 583 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 584 585 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 586 // for constrained LR/SC loop 587 val LRSCCycles = 64 588 // for lr storm 589 val LRSCBackOff = 8 590 591 // cache hierarchy configurations 592 val l1BusDataWidth = 256 593 594 // load violation predict 595 val ResetTimeMax2Pow = 20 //1078576 596 val ResetTimeMin2Pow = 10 //1024 597 // wait table parameters 598 val WaitTableSize = 1024 599 val MemPredPCWidth = log2Up(WaitTableSize) 600 val LWTUse2BitCounter = true 601 // store set parameters 602 val SSITSize = WaitTableSize 603 val LFSTSize = 32 604 val SSIDWidth = log2Up(LFSTSize) 605 val LFSTWidth = 4 606 val StoreSetEnable = true // LWT will be disabled if SS is enabled 607 val LFSTEnable = false 608 609 val PCntIncrStep: Int = 6 610 val numPCntHc: Int = 25 611 val numPCntPtw: Int = 19 612 613 val numCSRPCntFrontend = 8 614 val numCSRPCntCtrl = 8 615 val numCSRPCntLsu = 8 616 val numCSRPCntHc = 5 617} 618