1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.backend.datapath.WakeUpConfig 46import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 47 48import scala.math.min 49 50case object XSTileKey extends Field[Seq[XSCoreParameters]] 51 52case object XSCoreParamsKey extends Field[XSCoreParameters] 53 54case class XSCoreParameters 55( 56 HasPrefetch: Boolean = false, 57 HartId: Int = 0, 58 XLEN: Int = 64, 59 VLEN: Int = 128, 60 ELEN: Int = 64, 61 HasMExtension: Boolean = true, 62 HasCExtension: Boolean = true, 63 HasDiv: Boolean = true, 64 HasICache: Boolean = true, 65 HasDCache: Boolean = true, 66 AddrBits: Int = 64, 67 VAddrBits: Int = 39, 68 HasFPU: Boolean = true, 69 HasVPU: Boolean = true, 70 HasCustomCSRCacheOp: Boolean = true, 71 FetchWidth: Int = 8, 72 AsidLength: Int = 16, 73 EnableBPU: Boolean = true, 74 EnableBPD: Boolean = true, 75 EnableRAS: Boolean = true, 76 EnableLB: Boolean = false, 77 EnableLoop: Boolean = true, 78 EnableSC: Boolean = true, 79 EnbaleTlbDebug: Boolean = false, 80 EnableJal: Boolean = false, 81 EnableFauFTB: Boolean = true, 82 UbtbGHRLength: Int = 4, 83 // HistoryLength: Int = 512, 84 EnableGHistDiff: Boolean = true, 85 EnableCommitGHistDiff: Boolean = true, 86 UbtbSize: Int = 256, 87 FtbSize: Int = 2048, 88 RasSize: Int = 32, 89 CacheLineSize: Int = 512, 90 FtbWays: Int = 4, 91 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 92 // Sets Hist Tag 93 // Seq(( 2048, 2, 8), 94 // ( 2048, 9, 8), 95 // ( 2048, 13, 8), 96 // ( 2048, 20, 8), 97 // ( 2048, 26, 8), 98 // ( 2048, 44, 8), 99 // ( 2048, 73, 8), 100 // ( 2048, 256, 8)), 101 Seq(( 4096, 8, 8), 102 ( 4096, 13, 8), 103 ( 4096, 32, 8), 104 ( 4096, 119, 8)), 105 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 256, 4, 9), 108 ( 256, 8, 9), 109 ( 512, 13, 9), 110 ( 512, 16, 9), 111 ( 512, 32, 9)), 112 SCNRows: Int = 512, 113 SCNTables: Int = 4, 114 SCCtrBits: Int = 6, 115 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 116 numBr: Int = 2, 117 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 118 ((resp_in: BranchPredictionResp, p: Parameters) => { 119 val ftb = Module(new FTB()(p)) 120 val ubtb =Module(new FauFTB()(p)) 121 // val bim = Module(new BIM()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(ubtb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 // ubtb.io.resp_in(0) := resp_in 129 // bim.io.resp_in(0) := ubtb.io.resp 130 // btb.io.resp_in(0) := bim.io.resp 131 // tage.io.resp_in(0) := btb.io.resp 132 // loop.io.resp_in(0) := tage.io.resp 133 ubtb.io.in.bits.resp_in(0) := resp_in 134 tage.io.in.bits.resp_in(0) := ubtb.io.out 135 ftb.io.in.bits.resp_in(0) := tage.io.out 136 ittage.io.in.bits.resp_in(0) := ftb.io.out 137 ras.io.in.bits.resp_in(0) := ittage.io.out 138 139 (preds, ras.io.out) 140 }), 141 IBufSize: Int = 48, 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 6, 145 MaxUopSize: Int = 65, 146 FtqSize: Int = 64, 147 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 148 IntLogicRegs: Int = 32, 149 FpLogicRegs: Int = 33, 150 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 151 VCONFIG_IDX: Int = 32, 152 NRPhyRegs: Int = 192, 153 IntPhyRegs: Int = 192, 154 VfPhyRegs: Int = 192, 155 VirtualLoadQueueSize: Int = 80, 156 LoadQueueRARSize: Int = 80, 157 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 158 RollbackGroupSize: Int = 8, 159 LoadQueueReplaySize: Int = 80, 160 LoadUncacheBufferSize: Int = 20, 161 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 162 StoreQueueSize: Int = 64, 163 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 164 StoreQueueForwardWithMask: Boolean = true, 165 VlsQueueSize: Int = 8, 166 RobSize: Int = 256, 167 RabSize: Int = 256, 168 dpParams: DispatchParameters = DispatchParameters( 169 IntDqSize = 16, 170 FpDqSize = 16, 171 LsDqSize = 16, 172 IntDqDeqWidth = 6, 173 FpDqDeqWidth = 6, 174 LsDqDeqWidth = 6, 175 ), 176 intPreg: PregParams = IntPregParams( 177 numEntries = 256, 178 numRead = 14, 179 numWrite = 8, 180 ), 181 vfPreg: VfPregParams = VfPregParams( 182 numEntries = 256, 183 numRead = 14, 184 numWrite = 8, 185 ), 186 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 187 LoadPipelineWidth: Int = 2, 188 StorePipelineWidth: Int = 2, 189 VecMemSrcInWidth: Int = 2, 190 VecMemInstWbWidth: Int = 1, 191 VecMemDispatchWidth: Int = 1, 192 StoreBufferSize: Int = 16, 193 StoreBufferThreshold: Int = 7, 194 EnsbufferWidth: Int = 2, 195 UncacheBufferSize: Int = 4, 196 EnableLoadToLoadForward: Boolean = true, 197 EnableFastForward: Boolean = false, 198 EnableLdVioCheckAfterReset: Boolean = true, 199 EnableSoftPrefetchAfterReset: Boolean = true, 200 EnableCacheErrorAfterReset: Boolean = true, 201 EnableDCacheWPU: Boolean = false, 202 EnableAccurateLoadError: Boolean = true, 203 EnableUncacheWriteOutstanding: Boolean = false, 204 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 205 ReSelectLen: Int = 7, // load replay queue replay select counter len 206 itlbParameters: TLBParameters = TLBParameters( 207 name = "itlb", 208 fetchi = true, 209 useDmode = false, 210 normalNWays = 32, 211 normalReplacer = Some("plru"), 212 superNWays = 4, 213 superReplacer = Some("plru") 214 ), 215 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 217 ldtlbParameters: TLBParameters = TLBParameters( 218 name = "ldtlb", 219 normalNSets = 64, 220 normalNWays = 1, 221 normalAssociative = "sa", 222 normalReplacer = Some("setplru"), 223 superNWays = 16, 224 normalAsVictim = true, 225 outReplace = false, 226 partialStaticPMP = true, 227 outsideRecvFlush = true, 228 saveLevel = true 229 ), 230 sttlbParameters: TLBParameters = TLBParameters( 231 name = "sttlb", 232 normalNSets = 64, 233 normalNWays = 1, 234 normalAssociative = "sa", 235 normalReplacer = Some("setplru"), 236 superNWays = 16, 237 normalAsVictim = true, 238 outReplace = false, 239 partialStaticPMP = true, 240 outsideRecvFlush = true, 241 saveLevel = true 242 ), 243 pftlbParameters: TLBParameters = TLBParameters( 244 name = "pftlb", 245 normalNSets = 64, 246 normalNWays = 1, 247 normalAssociative = "sa", 248 normalReplacer = Some("setplru"), 249 superNWays = 16, 250 normalAsVictim = true, 251 outReplace = false, 252 partialStaticPMP = true, 253 outsideRecvFlush = true, 254 saveLevel = true 255 ), 256 refillBothTlb: Boolean = false, 257 btlbParameters: TLBParameters = TLBParameters( 258 name = "btlb", 259 normalNSets = 1, 260 normalNWays = 64, 261 superNWays = 4, 262 ), 263 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 264 NumPerfCounters: Int = 16, 265 icacheParameters: ICacheParameters = ICacheParameters( 266 tagECC = Some("parity"), 267 dataECC = Some("parity"), 268 replacer = Some("setplru"), 269 nMissEntries = 2, 270 nProbeEntries = 2, 271 nPrefetchEntries = 12, 272 nPrefBufferEntries = 64, 273 hasPrefetch = true, 274 ), 275 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 276 tagECC = Some("secded"), 277 dataECC = Some("secded"), 278 replacer = Some("setplru"), 279 nMissEntries = 16, 280 nProbeEntries = 8, 281 nReleaseEntries = 18 282 )), 283 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 284 name = "l2", 285 ways = 8, 286 sets = 1024, // default 512KB L2 287 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 288 )), 289 L2NBanks: Int = 1, 290 usePTWRepeater: Boolean = false, 291 softTLB: Boolean = false, // dpi-c l1tlb debug only 292 softPTW: Boolean = false, // dpi-c l2tlb debug only 293 softPTWDelay: Int = 1 294){ 295 def vlWidth = log2Up(VLEN) + 1 296 297 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 298 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 299 300 def intSchdParams = { 301 implicit val schdType: SchedulerType = IntScheduler() 302 val pregBits = intPreg.addrWidth 303 val numRfRead = intPreg.numRead 304 val numRfWrite = intPreg.numWrite 305 SchdBlockParams(Seq( 306 IssueBlockParams(Seq( 307 ExeUnitParams("IEX0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 308 ExeUnitParams("IEX1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 309 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 310 IssueBlockParams(Seq( 311 ExeUnitParams("IEX2", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 312 ExeUnitParams("IEX3", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 313 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 314 IssueBlockParams(Seq( 315 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 316 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 317 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 318 IssueBlockParams(Seq( 319 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 320 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 321 IssueBlockParams(Seq( 322 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 323 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 324 ), 325 numPregs = intPreg.numEntries, 326 numRfReadWrite = Some((numRfRead, numRfWrite)), 327 numDeqOutside = 0, 328 schdType = schdType, 329 rfDataWidth = intPreg.dataCfg.dataWidth, 330 numUopIn = dpParams.IntDqDeqWidth, 331 ) 332 } 333 def vfSchdParams = { 334 implicit val schdType: SchedulerType = VfScheduler() 335 val pregBits = vfPreg.addrWidth 336 val numRfRead = vfPreg.numRead 337 val numRfWrite = vfPreg.numWrite 338 SchdBlockParams(Seq( 339 IssueBlockParams(Seq( 340 ExeUnitParams("VEX0", Seq(VialuCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 341 ExeUnitParams("VEX1", Seq(VimacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 342 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 343 IssueBlockParams(Seq( 344 ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))), 345 ExeUnitParams("FEX1", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(VfRD(6, 0)))), 346 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 347 IssueBlockParams(Seq( 348 ExeUnitParams("FEX2", Seq(FDivSqrtCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(11, 0)), Seq(VfRD(12, 0)))), 349 ExeUnitParams("FEX3", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)))), 350 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 351 IssueBlockParams(Seq( 352 ExeUnitParams("VEX2", Seq(VppuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 353 ExeUnitParams("VEX3", Seq(VipuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 354 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 355 IssueBlockParams(Seq( 356 ExeUnitParams("VEX2", Seq(VfaluCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 357 ExeUnitParams("VEX3", Seq(VfmaCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 358 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 359 IssueBlockParams(Seq( 360 ExeUnitParams("VEX4", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 361 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 362 ), 363 numPregs = vfPreg.numEntries, 364 numRfReadWrite = Some((numRfRead, numRfWrite)), 365 numDeqOutside = 0, 366 schdType = schdType, 367 rfDataWidth = vfPreg.dataCfg.dataWidth, 368 numUopIn = dpParams.FpDqDeqWidth, 369 ) 370 } 371 def memSchdParams = { 372 implicit val schdType: SchedulerType = MemScheduler() 373 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 374 val rfDataWidth = 64 375 376 SchdBlockParams(Seq( 377 IssueBlockParams(Seq( 378 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 379 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 380 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 381 IssueBlockParams(Seq( 382 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))), 383 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))), 384 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 385 IssueBlockParams(Seq( 386 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 387 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(13, Int.MaxValue)))), 388 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 389 IssueBlockParams(Seq( 390 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 391 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 392 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 393 ), 394 numPregs = intPreg.numEntries max vfPreg.numEntries, 395 numRfReadWrite = None, 396 numDeqOutside = 0, 397 schdType = schdType, 398 rfDataWidth = rfDataWidth, 399 numUopIn = dpParams.LsDqDeqWidth, 400 ) 401 } 402 403 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 404 405 def iqWakeUpParams = { 406 Seq( 407 WakeUpConfig("IEX0" -> "IEX0"), 408 WakeUpConfig("IEX0" -> "IEX1"), 409 WakeUpConfig("IEX1" -> "IEX0"), 410 WakeUpConfig("IEX1" -> "IEX1"), 411 WakeUpConfig("IEX0" -> "BJU0"), 412 WakeUpConfig("IEX0" -> "BJU1"), 413 WakeUpConfig("IEX1" -> "BJU0"), 414 WakeUpConfig("IEX1" -> "BJU1"), 415 WakeUpConfig("IEX0" -> "LDU0"), 416 WakeUpConfig("IEX0" -> "LDU1"), 417 WakeUpConfig("IEX1" -> "LDU0"), 418 WakeUpConfig("IEX1" -> "LDU1"), 419 WakeUpConfig("IEX0" -> "STA0"), 420 WakeUpConfig("IEX0" -> "STA1"), 421 WakeUpConfig("IEX1" -> "STA0"), 422 WakeUpConfig("IEX1" -> "STA1"), 423 WakeUpConfig("IMISC0" -> "FEX0"), 424 WakeUpConfig("IMISC0" -> "FEX1"), 425 WakeUpConfig("IMISC0" -> "FEX2"), 426 WakeUpConfig("IMISC0" -> "FEX3"), 427 WakeUpConfig("IMISC0" -> "FEX4"), 428 WakeUpConfig("FEX3" -> "FEX0"), 429 WakeUpConfig("FEX3" -> "FEX1"), 430 WakeUpConfig("FEX3" -> "FEX2"), 431 WakeUpConfig("FEX3" -> "FEX3"), 432 ) 433 } 434 435 def backendParams: BackendParams = backend.BackendParams( 436 Map( 437 IntScheduler() -> intSchdParams, 438 VfScheduler() -> vfSchdParams, 439 MemScheduler() -> memSchdParams, 440 ), 441 Seq( 442 intPreg, 443 vfPreg, 444 ), 445 iqWakeUpParams, 446 ) 447} 448 449case object DebugOptionsKey extends Field[DebugOptions] 450 451case class DebugOptions 452( 453 FPGAPlatform: Boolean = false, 454 EnableDifftest: Boolean = false, 455 AlwaysBasicDiff: Boolean = true, 456 EnableDebug: Boolean = false, 457 EnablePerfDebug: Boolean = true, 458 UseDRAMSim: Boolean = false, 459 EnableConstantin: Boolean = false, 460 EnableTopDown: Boolean = false 461) 462 463trait HasXSParameter { 464 465 implicit val p: Parameters 466 467 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 468 469 val coreParams = p(XSCoreParamsKey) 470 val env = p(DebugOptionsKey) 471 472 val XLEN = coreParams.XLEN 473 val VLEN = coreParams.VLEN 474 val ELEN = coreParams.ELEN 475 val minFLen = 32 476 val fLen = 64 477 def xLen = XLEN 478 479 val HasMExtension = coreParams.HasMExtension 480 val HasCExtension = coreParams.HasCExtension 481 val HasDiv = coreParams.HasDiv 482 val HasIcache = coreParams.HasICache 483 val HasDcache = coreParams.HasDCache 484 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 485 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 486 val AsidLength = coreParams.AsidLength 487 val ReSelectLen = coreParams.ReSelectLen 488 val AddrBytes = AddrBits / 8 // unused 489 val DataBits = XLEN 490 val DataBytes = DataBits / 8 491 val HasFPU = coreParams.HasFPU 492 val HasVPU = coreParams.HasVPU 493 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 494 val FetchWidth = coreParams.FetchWidth 495 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 496 val EnableBPU = coreParams.EnableBPU 497 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 498 val EnableRAS = coreParams.EnableRAS 499 val EnableLB = coreParams.EnableLB 500 val EnableLoop = coreParams.EnableLoop 501 val EnableSC = coreParams.EnableSC 502 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 503 val HistoryLength = coreParams.HistoryLength 504 val EnableGHistDiff = coreParams.EnableGHistDiff 505 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 506 val UbtbGHRLength = coreParams.UbtbGHRLength 507 val UbtbSize = coreParams.UbtbSize 508 val EnableFauFTB = coreParams.EnableFauFTB 509 val FtbSize = coreParams.FtbSize 510 val FtbWays = coreParams.FtbWays 511 val RasSize = coreParams.RasSize 512 513 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 514 coreParams.branchPredictor(resp_in, p) 515 } 516 val numBr = coreParams.numBr 517 val TageTableInfos = coreParams.TageTableInfos 518 val TageBanks = coreParams.numBr 519 val SCNRows = coreParams.SCNRows 520 val SCCtrBits = coreParams.SCCtrBits 521 val SCHistLens = coreParams.SCHistLens 522 val SCNTables = coreParams.SCNTables 523 524 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 525 case ((n, cb), h) => (n, cb, h) 526 } 527 val ITTageTableInfos = coreParams.ITTageTableInfos 528 type FoldedHistoryInfo = Tuple2[Int, Int] 529 val foldedGHistInfos = 530 (TageTableInfos.map{ case (nRows, h, t) => 531 if (h > 0) 532 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 533 else 534 Set[FoldedHistoryInfo]() 535 }.reduce(_++_).toSet ++ 536 SCTableInfos.map{ case (nRows, _, h) => 537 if (h > 0) 538 Set((h, min(log2Ceil(nRows/TageBanks), h))) 539 else 540 Set[FoldedHistoryInfo]() 541 }.reduce(_++_).toSet ++ 542 ITTageTableInfos.map{ case (nRows, h, t) => 543 if (h > 0) 544 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 545 else 546 Set[FoldedHistoryInfo]() 547 }.reduce(_++_) ++ 548 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 549 ).toList 550 551 552 553 val CacheLineSize = coreParams.CacheLineSize 554 val CacheLineHalfWord = CacheLineSize / 16 555 val ExtHistoryLength = HistoryLength + 64 556 val IBufSize = coreParams.IBufSize 557 val DecodeWidth = coreParams.DecodeWidth 558 val RenameWidth = coreParams.RenameWidth 559 val CommitWidth = coreParams.CommitWidth 560 val MaxUopSize = coreParams.MaxUopSize 561 val FtqSize = coreParams.FtqSize 562 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 563 val IntLogicRegs = coreParams.IntLogicRegs 564 val FpLogicRegs = coreParams.FpLogicRegs 565 val VecLogicRegs = coreParams.VecLogicRegs 566 val VCONFIG_IDX = coreParams.VCONFIG_IDX 567 val NRPhyRegs = coreParams.NRPhyRegs 568 val PhyRegIdxWidth = log2Up(NRPhyRegs) 569 val IntPhyRegs = coreParams.IntPhyRegs 570 val VfPhyRegs = coreParams.VfPhyRegs 571 val IntPregIdxWidth = log2Up(IntPhyRegs) 572 val VfPregIdxWidth = log2Up(VfPhyRegs) 573 val RobSize = coreParams.RobSize 574 val RabSize = coreParams.RabSize 575 val IntRefCounterWidth = log2Ceil(RobSize) 576 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 577 val LoadQueueRARSize = coreParams.LoadQueueRARSize 578 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 579 val RollbackGroupSize = coreParams.RollbackGroupSize 580 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 581 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 582 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 583 val StoreQueueSize = coreParams.StoreQueueSize 584 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 585 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 586 val VlsQueueSize = coreParams.VlsQueueSize 587 val dpParams = coreParams.dpParams 588 589 def backendParams: BackendParams = coreParams.backendParams 590 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 591 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 592 val LoadPipelineWidth = coreParams.LoadPipelineWidth 593 val StorePipelineWidth = coreParams.StorePipelineWidth 594 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 595 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 596 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 597 val StoreBufferSize = coreParams.StoreBufferSize 598 val StoreBufferThreshold = coreParams.StoreBufferThreshold 599 val EnsbufferWidth = coreParams.EnsbufferWidth 600 val UncacheBufferSize = coreParams.UncacheBufferSize 601 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 602 val EnableFastForward = coreParams.EnableFastForward 603 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 604 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 605 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 606 val EnableDCacheWPU = coreParams.EnableDCacheWPU 607 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 608 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 609 val asidLen = coreParams.MMUAsidLen 610 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 611 val refillBothTlb = coreParams.refillBothTlb 612 val itlbParams = coreParams.itlbParameters 613 val ldtlbParams = coreParams.ldtlbParameters 614 val sttlbParams = coreParams.sttlbParameters 615 val pftlbParams = coreParams.pftlbParameters 616 val btlbParams = coreParams.btlbParameters 617 val l2tlbParams = coreParams.l2tlbParameters 618 val NumPerfCounters = coreParams.NumPerfCounters 619 620 val instBytes = if (HasCExtension) 2 else 4 621 val instOffsetBits = log2Ceil(instBytes) 622 623 val icacheParameters = coreParams.icacheParameters 624 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 625 626 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 627 // for constrained LR/SC loop 628 val LRSCCycles = 64 629 // for lr storm 630 val LRSCBackOff = 8 631 632 // cache hierarchy configurations 633 val l1BusDataWidth = 256 634 635 // load violation predict 636 val ResetTimeMax2Pow = 20 //1078576 637 val ResetTimeMin2Pow = 10 //1024 638 // wait table parameters 639 val WaitTableSize = 1024 640 val MemPredPCWidth = log2Up(WaitTableSize) 641 val LWTUse2BitCounter = true 642 // store set parameters 643 val SSITSize = WaitTableSize 644 val LFSTSize = 32 645 val SSIDWidth = log2Up(LFSTSize) 646 val LFSTWidth = 4 647 val StoreSetEnable = true // LWT will be disabled if SS is enabled 648 val LFSTEnable = false 649 650 val PCntIncrStep: Int = 6 651 val numPCntHc: Int = 25 652 val numPCntPtw: Int = 19 653 654 val numCSRPCntFrontend = 8 655 val numCSRPCntCtrl = 8 656 val numCSRPCntLsu = 8 657 val numCSRPCntHc = 5 658 659 // source stages of cancel signal to issue queues 660 val cancelStages = Seq("IS", "OG0", "OG1") 661} 662