1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 46 47import scala.math.min 48 49case object XSTileKey extends Field[Seq[XSCoreParameters]] 50 51case object XSCoreParamsKey extends Field[XSCoreParameters] 52 53case class XSCoreParameters 54( 55 HasPrefetch: Boolean = false, 56 HartId: Int = 0, 57 XLEN: Int = 64, 58 VLEN: Int = 128, 59 ELEN: Int = 64, 60 HasMExtension: Boolean = true, 61 HasCExtension: Boolean = true, 62 HasDiv: Boolean = true, 63 HasICache: Boolean = true, 64 HasDCache: Boolean = true, 65 AddrBits: Int = 64, 66 VAddrBits: Int = 39, 67 HasFPU: Boolean = true, 68 HasVPU: Boolean = true, 69 HasCustomCSRCacheOp: Boolean = true, 70 FetchWidth: Int = 8, 71 AsidLength: Int = 16, 72 EnableBPU: Boolean = true, 73 EnableBPD: Boolean = true, 74 EnableRAS: Boolean = true, 75 EnableLB: Boolean = false, 76 EnableLoop: Boolean = true, 77 EnableSC: Boolean = true, 78 EnbaleTlbDebug: Boolean = false, 79 EnableJal: Boolean = false, 80 EnableFauFTB: Boolean = true, 81 UbtbGHRLength: Int = 4, 82 // HistoryLength: Int = 512, 83 EnableGHistDiff: Boolean = true, 84 EnableCommitGHistDiff: Boolean = true, 85 UbtbSize: Int = 256, 86 FtbSize: Int = 2048, 87 RasSize: Int = 32, 88 CacheLineSize: Int = 512, 89 FtbWays: Int = 4, 90 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 // Seq(( 2048, 2, 8), 93 // ( 2048, 9, 8), 94 // ( 2048, 13, 8), 95 // ( 2048, 20, 8), 96 // ( 2048, 26, 8), 97 // ( 2048, 44, 8), 98 // ( 2048, 73, 8), 99 // ( 2048, 256, 8)), 100 Seq(( 4096, 8, 8), 101 ( 4096, 13, 8), 102 ( 4096, 32, 8), 103 ( 4096, 119, 8)), 104 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 256, 4, 9), 107 ( 256, 8, 9), 108 ( 512, 13, 9), 109 ( 512, 16, 9), 110 ( 512, 32, 9)), 111 SCNRows: Int = 512, 112 SCNTables: Int = 4, 113 SCCtrBits: Int = 6, 114 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 115 numBr: Int = 2, 116 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 117 ((resp_in: BranchPredictionResp, p: Parameters) => { 118 val ftb = Module(new FTB()(p)) 119 val ubtb =Module(new FauFTB()(p)) 120 // val bim = Module(new BIM()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(ubtb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 // ubtb.io.resp_in(0) := resp_in 128 // bim.io.resp_in(0) := ubtb.io.resp 129 // btb.io.resp_in(0) := bim.io.resp 130 // tage.io.resp_in(0) := btb.io.resp 131 // loop.io.resp_in(0) := tage.io.resp 132 ubtb.io.in.bits.resp_in(0) := resp_in 133 tage.io.in.bits.resp_in(0) := ubtb.io.out 134 ftb.io.in.bits.resp_in(0) := tage.io.out 135 ittage.io.in.bits.resp_in(0) := ftb.io.out 136 ras.io.in.bits.resp_in(0) := ittage.io.out 137 138 (preds, ras.io.out) 139 }), 140 IBufSize: Int = 48, 141 DecodeWidth: Int = 6, 142 RenameWidth: Int = 6, 143 CommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 FtqSize: Int = 64, 146 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 147 IntLogicRegs: Int = 32, 148 FpLogicRegs: Int = 33, 149 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 150 VCONFIG_IDX: Int = 32, 151 NRPhyRegs: Int = 192, 152 IntPhyRegs: Int = 192, 153 VfPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 80, 155 LoadQueueRARSize: Int = 80, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 80, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 256, 166 RabSize: Int = 256, 167 dpParams: DispatchParameters = DispatchParameters( 168 IntDqSize = 16, 169 FpDqSize = 16, 170 LsDqSize = 16, 171 IntDqDeqWidth = 6, 172 FpDqDeqWidth = 6, 173 LsDqDeqWidth = 6, 174 ), 175 intPreg: PregParams = IntPregParams( 176 numEntries = 256, 177 numRead = 14, 178 numWrite = 8, 179 ), 180 vfPreg: VfPregParams = VfPregParams( 181 numEntries = 256, 182 numRead = 14, 183 numWrite = 8, 184 ), 185 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 186 LoadPipelineWidth: Int = 2, 187 StorePipelineWidth: Int = 2, 188 VecMemSrcInWidth: Int = 2, 189 VecMemInstWbWidth: Int = 1, 190 VecMemDispatchWidth: Int = 1, 191 StoreBufferSize: Int = 16, 192 StoreBufferThreshold: Int = 7, 193 EnsbufferWidth: Int = 2, 194 UncacheBufferSize: Int = 4, 195 EnableLoadToLoadForward: Boolean = true, 196 EnableFastForward: Boolean = false, 197 EnableLdVioCheckAfterReset: Boolean = true, 198 EnableSoftPrefetchAfterReset: Boolean = true, 199 EnableCacheErrorAfterReset: Boolean = true, 200 EnableDCacheWPU: Boolean = false, 201 EnableAccurateLoadError: Boolean = true, 202 EnableUncacheWriteOutstanding: Boolean = false, 203 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 204 ReSelectLen: Int = 7, // load replay queue replay select counter len 205 itlbParameters: TLBParameters = TLBParameters( 206 name = "itlb", 207 fetchi = true, 208 useDmode = false, 209 normalNWays = 32, 210 normalReplacer = Some("plru"), 211 superNWays = 4, 212 superReplacer = Some("plru") 213 ), 214 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ldtlbParameters: TLBParameters = TLBParameters( 217 name = "ldtlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 sttlbParameters: TLBParameters = TLBParameters( 230 name = "sttlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 pftlbParameters: TLBParameters = TLBParameters( 243 name = "pftlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 refillBothTlb: Boolean = false, 256 btlbParameters: TLBParameters = TLBParameters( 257 name = "btlb", 258 normalNSets = 1, 259 normalNWays = 64, 260 superNWays = 4, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 64, 272 hasPrefetch = true, 273 ), 274 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 275 tagECC = Some("secded"), 276 dataECC = Some("secded"), 277 replacer = Some("setplru"), 278 nMissEntries = 16, 279 nProbeEntries = 8, 280 nReleaseEntries = 18 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 def vlWidth = log2Up(VLEN) + 1 295 296 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 297 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 298 299 def intSchdParams = { 300 implicit val schdType: SchedulerType = IntScheduler() 301 val pregBits = intPreg.addrWidth 302 val numRfRead = intPreg.numRead 303 val numRfWrite = intPreg.numWrite 304 SchdBlockParams(Seq( 305 IssueBlockParams(Seq( 306 ExeUnitParams("IEX0", Seq(AluCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(2, 2)), Seq(IntRD(3, 2)))), 307 ExeUnitParams("IEX1", Seq(AluCfg), Seq(IntWB(port = 3, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 308 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams("IEX2", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 311 ExeUnitParams("IEX3", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 312 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 315 ExeUnitParams("IDIV1", Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 319 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 320 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 321 IssueBlockParams(Seq( 322 ExeUnitParams("IMISC0", Seq(I2fCfg, VSetRiWiCfg), Seq(VfWB(port = 3, Int.MaxValue), IntWB(port = 1, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 323 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 324 IssueBlockParams(Seq( 325 ExeUnitParams("IMISC1", Seq(VSetRiWvfCfg), Seq(VfWB(port = 3, Int.MaxValue)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 326 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 327 ), 328 numPregs = intPreg.numEntries, 329 numRfReadWrite = Some((numRfRead, numRfWrite)), 330 numDeqOutside = 0, 331 schdType = schdType, 332 rfDataWidth = intPreg.dataCfg.dataWidth, 333 numUopIn = dpParams.IntDqDeqWidth, 334 ) 335 } 336 def vfSchdParams = { 337 implicit val schdType: SchedulerType = VfScheduler() 338 val pregBits = vfPreg.addrWidth 339 val numRfRead = vfPreg.numRead 340 val numRfWrite = vfPreg.numWrite 341 SchdBlockParams(Seq( 342 IssueBlockParams(Seq( 343 ExeUnitParams("VEX0", Seq(VialuCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 344 ExeUnitParams("VEX1", Seq(VimacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 345 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 346 IssueBlockParams(Seq( 347 ExeUnitParams("VEX2", Seq(VppuCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 348 ExeUnitParams("VEX3", Seq(VipuCfg), Seq(VfWB(port = 7, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 349 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 350 IssueBlockParams(Seq( 351 ExeUnitParams("VEX4", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 352 ExeUnitParams("VEX5", Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 0, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 353 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 354 IssueBlockParams(Seq( 355 ExeUnitParams("VEX6", Seq(VfaluCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 356 ExeUnitParams("VEX7", Seq(VfmaCfg) , Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 357 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 358 ), 359 numPregs = vfPreg.numEntries, 360 numRfReadWrite = Some((numRfRead, numRfWrite)), 361 numDeqOutside = 0, 362 schdType = schdType, 363 rfDataWidth = vfPreg.dataCfg.dataWidth, 364 numUopIn = dpParams.FpDqDeqWidth, 365 ) 366 } 367 def memSchdParams = { 368 implicit val schdType: SchedulerType = MemScheduler() 369 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 370 val rfDataWidth = 64 371 372 SchdBlockParams(Seq( 373 IssueBlockParams(Seq( 374 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 375 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 376 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 377 IssueBlockParams(Seq( 378 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 379 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 380 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 381 IssueBlockParams(Seq( 382 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 383 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 384 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 385 IssueBlockParams(Seq( 386 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 387 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 0)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 388 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 389 ), 390 numPregs = intPreg.numEntries max vfPreg.numEntries, 391 numRfReadWrite = None, 392 numDeqOutside = 0, 393 schdType = schdType, 394 rfDataWidth = rfDataWidth, 395 numUopIn = dpParams.LsDqDeqWidth, 396 ) 397 } 398 399 def backendParams: BackendParams = backend.BackendParams(Map( 400 IntScheduler() -> intSchdParams, 401 VfScheduler() -> vfSchdParams, 402 MemScheduler() -> memSchdParams, 403 ), Seq( 404 intPreg, 405 vfPreg, 406 )) 407} 408 409case object DebugOptionsKey extends Field[DebugOptions] 410 411case class DebugOptions 412( 413 FPGAPlatform: Boolean = false, 414 EnableDifftest: Boolean = false, 415 AlwaysBasicDiff: Boolean = true, 416 EnableDebug: Boolean = false, 417 EnablePerfDebug: Boolean = true, 418 UseDRAMSim: Boolean = false, 419 EnableConstantin: Boolean = false, 420 EnableTopDown: Boolean = false 421) 422 423trait HasXSParameter { 424 425 implicit val p: Parameters 426 427 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 428 429 val coreParams = p(XSCoreParamsKey) 430 val env = p(DebugOptionsKey) 431 432 val XLEN = coreParams.XLEN 433 val VLEN = coreParams.VLEN 434 val ELEN = coreParams.ELEN 435 val minFLen = 32 436 val fLen = 64 437 def xLen = XLEN 438 439 val HasMExtension = coreParams.HasMExtension 440 val HasCExtension = coreParams.HasCExtension 441 val HasDiv = coreParams.HasDiv 442 val HasIcache = coreParams.HasICache 443 val HasDcache = coreParams.HasDCache 444 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 445 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 446 val AsidLength = coreParams.AsidLength 447 val ReSelectLen = coreParams.ReSelectLen 448 val AddrBytes = AddrBits / 8 // unused 449 val DataBits = XLEN 450 val DataBytes = DataBits / 8 451 val HasFPU = coreParams.HasFPU 452 val HasVPU = coreParams.HasVPU 453 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 454 val FetchWidth = coreParams.FetchWidth 455 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 456 val EnableBPU = coreParams.EnableBPU 457 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 458 val EnableRAS = coreParams.EnableRAS 459 val EnableLB = coreParams.EnableLB 460 val EnableLoop = coreParams.EnableLoop 461 val EnableSC = coreParams.EnableSC 462 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 463 val HistoryLength = coreParams.HistoryLength 464 val EnableGHistDiff = coreParams.EnableGHistDiff 465 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 466 val UbtbGHRLength = coreParams.UbtbGHRLength 467 val UbtbSize = coreParams.UbtbSize 468 val EnableFauFTB = coreParams.EnableFauFTB 469 val FtbSize = coreParams.FtbSize 470 val FtbWays = coreParams.FtbWays 471 val RasSize = coreParams.RasSize 472 473 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 474 coreParams.branchPredictor(resp_in, p) 475 } 476 val numBr = coreParams.numBr 477 val TageTableInfos = coreParams.TageTableInfos 478 val TageBanks = coreParams.numBr 479 val SCNRows = coreParams.SCNRows 480 val SCCtrBits = coreParams.SCCtrBits 481 val SCHistLens = coreParams.SCHistLens 482 val SCNTables = coreParams.SCNTables 483 484 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 485 case ((n, cb), h) => (n, cb, h) 486 } 487 val ITTageTableInfos = coreParams.ITTageTableInfos 488 type FoldedHistoryInfo = Tuple2[Int, Int] 489 val foldedGHistInfos = 490 (TageTableInfos.map{ case (nRows, h, t) => 491 if (h > 0) 492 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 493 else 494 Set[FoldedHistoryInfo]() 495 }.reduce(_++_).toSet ++ 496 SCTableInfos.map{ case (nRows, _, h) => 497 if (h > 0) 498 Set((h, min(log2Ceil(nRows/TageBanks), h))) 499 else 500 Set[FoldedHistoryInfo]() 501 }.reduce(_++_).toSet ++ 502 ITTageTableInfos.map{ case (nRows, h, t) => 503 if (h > 0) 504 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 505 else 506 Set[FoldedHistoryInfo]() 507 }.reduce(_++_) ++ 508 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 509 ).toList 510 511 512 513 val CacheLineSize = coreParams.CacheLineSize 514 val CacheLineHalfWord = CacheLineSize / 16 515 val ExtHistoryLength = HistoryLength + 64 516 val IBufSize = coreParams.IBufSize 517 val DecodeWidth = coreParams.DecodeWidth 518 val RenameWidth = coreParams.RenameWidth 519 val CommitWidth = coreParams.CommitWidth 520 val MaxUopSize = coreParams.MaxUopSize 521 val FtqSize = coreParams.FtqSize 522 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 523 val IntLogicRegs = coreParams.IntLogicRegs 524 val FpLogicRegs = coreParams.FpLogicRegs 525 val VecLogicRegs = coreParams.VecLogicRegs 526 val VCONFIG_IDX = coreParams.VCONFIG_IDX 527 val NRPhyRegs = coreParams.NRPhyRegs 528 val PhyRegIdxWidth = log2Up(NRPhyRegs) 529 val IntPhyRegs = coreParams.IntPhyRegs 530 val VfPhyRegs = coreParams.VfPhyRegs 531 val IntPregIdxWidth = log2Up(IntPhyRegs) 532 val VfPregIdxWidth = log2Up(VfPhyRegs) 533 val RobSize = coreParams.RobSize 534 val RabSize = coreParams.RabSize 535 val IntRefCounterWidth = log2Ceil(RobSize) 536 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 537 val LoadQueueRARSize = coreParams.LoadQueueRARSize 538 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 539 val RollbackGroupSize = coreParams.RollbackGroupSize 540 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 541 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 542 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 543 val StoreQueueSize = coreParams.StoreQueueSize 544 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 545 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 546 val VlsQueueSize = coreParams.VlsQueueSize 547 val dpParams = coreParams.dpParams 548 549 def backendParams: BackendParams = coreParams.backendParams 550 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 551 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 552 val LoadPipelineWidth = coreParams.LoadPipelineWidth 553 val StorePipelineWidth = coreParams.StorePipelineWidth 554 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 555 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 556 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 557 val StoreBufferSize = coreParams.StoreBufferSize 558 val StoreBufferThreshold = coreParams.StoreBufferThreshold 559 val EnsbufferWidth = coreParams.EnsbufferWidth 560 val UncacheBufferSize = coreParams.UncacheBufferSize 561 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 562 val EnableFastForward = coreParams.EnableFastForward 563 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 564 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 565 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 566 val EnableDCacheWPU = coreParams.EnableDCacheWPU 567 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 568 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 569 val asidLen = coreParams.MMUAsidLen 570 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 571 val refillBothTlb = coreParams.refillBothTlb 572 val itlbParams = coreParams.itlbParameters 573 val ldtlbParams = coreParams.ldtlbParameters 574 val sttlbParams = coreParams.sttlbParameters 575 val pftlbParams = coreParams.pftlbParameters 576 val btlbParams = coreParams.btlbParameters 577 val l2tlbParams = coreParams.l2tlbParameters 578 val NumPerfCounters = coreParams.NumPerfCounters 579 580 val instBytes = if (HasCExtension) 2 else 4 581 val instOffsetBits = log2Ceil(instBytes) 582 583 val icacheParameters = coreParams.icacheParameters 584 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 585 586 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 587 // for constrained LR/SC loop 588 val LRSCCycles = 64 589 // for lr storm 590 val LRSCBackOff = 8 591 592 // cache hierarchy configurations 593 val l1BusDataWidth = 256 594 595 // load violation predict 596 val ResetTimeMax2Pow = 20 //1078576 597 val ResetTimeMin2Pow = 10 //1024 598 // wait table parameters 599 val WaitTableSize = 1024 600 val MemPredPCWidth = log2Up(WaitTableSize) 601 val LWTUse2BitCounter = true 602 // store set parameters 603 val SSITSize = WaitTableSize 604 val LFSTSize = 32 605 val SSIDWidth = log2Up(LFSTSize) 606 val LFSTWidth = 4 607 val StoreSetEnable = true // LWT will be disabled if SS is enabled 608 val LFSTEnable = false 609 610 val PCntIncrStep: Int = 6 611 val numPCntHc: Int = 25 612 val numPCntPtw: Int = 19 613 614 val numCSRPCntFrontend = 8 615 val numCSRPCntCtrl = 8 616 val numCSRPCntLsu = 8 617 val numCSRPCntHc = 5 618} 619