| #
67fcf090 |
| 18-Apr-2023 |
Xuan Hu <[email protected]> |
Merge remote-tracking branch 'upstream/master' into new-backend
|
| #
730cfbc0 |
| 16-Apr-2023 |
Xuan Hu <[email protected]> |
backend: merge v2backend into backend
|
| #
124bf66a |
| 12-Apr-2023 |
Xuan Hu <[email protected]> |
backend,Core: remove dead code and comments
|
| #
7720a376 |
| 12-Apr-2023 |
fdy <[email protected]> |
Decode: change ListLookup to DecodeLogic
|
| #
cee61068 |
| 12-Apr-2023 |
fdy <[email protected]> |
DataPath: add regfile read arbiter
|
| #
965c972c |
| 10-Apr-2023 |
Xuan Hu <[email protected]> |
backend: fix iq issued setting bug again
* pass riscv-tests rv64ui, um tests
|
| #
61d88ec2 |
| 06-Apr-2023 |
Xuan Hu <[email protected]> |
backend: fix iq issued setting bug
* issued should be set to false when not stage success
|
| #
92bbe188 |
| 05-Apr-2023 |
Xuan Hu <[email protected]> |
backend,memBlock: move `rsIdx` into uop bundle
* `rsIdx` and `isFirstIssue` should be guarded by valid instead connecting from IQ to memBlock directly.
|
| #
141a6449 |
| 27-Mar-2023 |
Xuan Hu <[email protected]> |
backend: add load inst support
|
| #
3d1a5c10 |
| 11-Mar-2023 |
maliao <[email protected]> |
Rob: Add Rab module to support separate commit of uops and instructions (#1956)
|
| #
6355a2b7 |
| 10-Mar-2023 |
czw <[email protected]> |
func(vxsat): add vxsat form VIPU to CSR
|
| #
f6e6a345 |
| 09-Mar-2023 |
czw <[email protected]> |
func(uopIdx): add end flag for uopIdx
1. add end flag for uopIdx
2. fix(VFPU): io.in.ready should be ture.B
3. func(VIAlu):add VIAlu code v2
|
| #
1a0debc2 |
| 08-Mar-2023 |
czw <[email protected]> |
func(vialu): add vialu & pass vadd (#1953)
|
| #
3b739f49 |
| 06-Mar-2023 |
Xuan Hu <[email protected]> |
v2backend: huge tmp commit
|
| #
822120df |
| 02-Mar-2023 |
czw <[email protected]> |
func(vmask): add vmask to the pipeline & support vmadc.vim
|
| #
acbea6c4 |
| 28-Feb-2023 |
zhanglyGit <[email protected]> |
add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div supporting(LMUL=8) (#1930)
* add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div support(LMUL=8)
* ch
add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div supporting(LMUL=8) (#1930)
* add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div support(LMUL=8)
* changes made to implement a uop Div supporting with a cleaner code style(support Config)
* MaxNumOfUop parameterization supporting
show more ...
|
| #
caa3d04a |
| 21-Feb-2023 |
ZhangZifei <[email protected]> |
Merge remote-tracking branch 'origin/master' into rf-after-issue
|
| #
8744445e |
| 15-Feb-2023 |
Maxpicca-Li <[email protected]> |
lsdb: add some information of ls instructions by chiselDB (#1900)
Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.
Former RTL
lsdb: add some information of ls instructions by chiselDB (#1900)
Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.
Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher
failed to receive prefetch train info from L1. This commit should fix that.
* ROB: add inst db drop
globalID signal output is still duplicated
* TLB: TLB will carry mem idx when req and resp
* InstDB: update the TLBFirstIssue
* InstDB: the first version is complete
* InstDB: update decode logic
* InstDB: update ctrlBlock writeback
* Merge: fix bug
* merge: fix compile bug
* code rule: rename debug signals and add db's FPGA signal control
* code rule: update db's FPGA signal control
* ldu: fix isFirstIssue flag for ldflow from rs
* ldu: isFirstIssue flag for hw pf is always false
---------
Co-authored-by: good-circle <[email protected]>
Co-authored-by: William Wang <[email protected]>
show more ...
|
| #
5bb56d4d |
| 12-Feb-2023 |
ZhangZifei <[email protected]> |
Merge remote-tracking branch 'origin/master' into rf-after-issue
|
| #
8a264e15 |
| 11-Feb-2023 |
maliao <[email protected]> |
vset: Use bundle(VConfig, VType) to replace vconfig's bitwise select (#1910)
|
| #
cbd13d6e |
| 10-Feb-2023 |
ZhangZifei <[email protected]> |
rs: fix bug of wakeup.vecMatch
|
| #
edbf1204 |
| 09-Oct-2022 |
LinJiawei <[email protected]> |
Added Stride Pf
|
| #
f1d78cf7 |
| 20-Sep-2022 |
LinJiawei <[email protected]> |
BOP: support only prefetch store
|
| #
5d13017e |
| 08-Sep-2022 |
LinJiawei <[email protected]> |
CSR: enable L1D prefetch by default
|
| #
85de5cae |
| 06-Sep-2022 |
LinJiawei <[email protected]> |
Add prefetch control; Update SMS algorithm
|