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/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
100 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
101 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
Damdgpu_gfx.c37 /* delay 0.1 second to enable gfx off feature */
43 * GPU GFX IP block helpers function.
51 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
52 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
53 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
62 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
63 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
64 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
65 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
66 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
[all …]
Dgfx_v12_0.c40 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
177 /* gfx queue registers */
310 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
378 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; in gfx_v12_0_set_kiq_pm4_funcs()
526 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v12_0_free_microcode()
527 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v12_0_free_microcode()
528 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v12_0_free_microcode()
529 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v12_0_free_microcode()
531 kfree(adev->gfx.rlc.register_list_format); in gfx_v12_0_free_microcode()
569 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v12_0_init_microcode()
[all …]
Dgfx_v11_0.c42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
218 /* gfx queue registers */
301 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
366 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
434 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
628 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
629 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
630 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
631 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
633 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
[all …]
Dgfx_v6_0.c339 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v6_0_init_microcode()
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
348 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v6_0_init_microcode()
353 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
354 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
355 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v6_0_init_microcode()
362 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
[all …]
Dgfx_v7_0.c889 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
890 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
891 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
892 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
936 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v7_0_init_microcode()
942 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v7_0_init_microcode()
954 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v7_0_init_microcode()
[all …]
Dgfx_v8_0.c927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
984 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
988 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
993 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
[all …]
Dgfx_v9_4_3.c34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_4_3_kiq_set_resources()
337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; in gfx_v9_4_3_set_kiq_pm4_funcs()
346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
519 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
523 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
530 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_4_3_free_microcode()
531 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_4_3_free_microcode()
532 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_4_3_free_microcode()
[all …]
Dgfx_v9_0.c46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
907 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_0_kiq_set_resources()
1066 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1256 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1257 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1258 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1259 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1260 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1261 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1263 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
[all …]
Damdgpu_dev_coredump.c88 adev->gfx.me_feature_version, adev->gfx.me_fw_version); in amdgpu_devcoredump_fw_info()
90 adev->gfx.pfp_feature_version, adev->gfx.pfp_fw_version); in amdgpu_devcoredump_fw_info()
92 adev->gfx.ce_feature_version, adev->gfx.ce_fw_version); in amdgpu_devcoredump_fw_info()
94 adev->gfx.rlc_feature_version, adev->gfx.rlc_fw_version); in amdgpu_devcoredump_fw_info()
97 adev->gfx.rlc_srlc_feature_version, in amdgpu_devcoredump_fw_info()
98 adev->gfx.rlc_srlc_fw_version); in amdgpu_devcoredump_fw_info()
100 adev->gfx.rlc_srlg_feature_version, in amdgpu_devcoredump_fw_info()
101 adev->gfx.rlc_srlg_fw_version); in amdgpu_devcoredump_fw_info()
103 adev->gfx.rlc_srls_feature_version, in amdgpu_devcoredump_fw_info()
104 adev->gfx.rlc_srls_fw_version); in amdgpu_devcoredump_fw_info()
[all …]
Damdgpu_atomfirmware.c825 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
826 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
827 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
828 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
829 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
830 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
831 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
832 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
833 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
835 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
[all …]
Damdgpu_kms.c233 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
234 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
237 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
238 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
241 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
242 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
245 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
246 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
249 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
250 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
[all …]
Dgfx_v10_0.c40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
429 /* gfx queue registers */
3685 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx10_kiq_set_resources()
3808 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
4049 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
4050 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
4051 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
4052 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
4053 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
4054 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
[all …]
Damdgpu_ucode.c109 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
127 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
749 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
750 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
751 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
752 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
753 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
754 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
755 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
756 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
[all …]
Damdgpu_gfx.h28 * GFX stuff
39 /* GFX current status */
165 * GFX configurations
223 /* gfx configure feature */
417 /* gfx status */
430 /* gfx off */
433 … gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: ad…
434 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
494 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
495 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((a…
[all …]
Damdgpu_debugfs.c130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
257 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_regs2_op()
433 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_gprwave_read()
434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
438 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
441 if (adev->gfx.funcs->read_wave_sgprs) in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
[all …]
Dimu_v11_0.c53 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, in imu_v11_0_init_microcode()
58 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
59 //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); in imu_v11_0_init_microcode()
64 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
69 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
73 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
80 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
92 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
95 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
98 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/gpu/
Daspeed-gfx.txt1 Device tree configuration for the GFX display device on the ASPEED SoCs
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
17 - resets: reset line that must be released to use the GFX device
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/linux-6.14.4/Documentation/ABI/testing/
Dsysfs-driver-intel-i915-hwmon4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
82 Contact: intel-gfx@lists.freedesktop.org
90 Contact: intel-gfx@lists.freedesktop.org
/linux-6.14.4/drivers/gpu/drm/ci/xfails/
Di915-amly-flakes.txt2 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
9 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
16 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
23 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
30 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
37 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
44 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
51 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
Damdgpu-stoney-flakes.txt2 # Bug Report: https://lore.kernel.org/amd-gfx/[email protected]/T/…
9 # Bug Report: https://lore.kernel.org/amd-gfx/[email protected]/T/…
16 # Bug Report: https://lore.kernel.org/amd-gfx/[email protected]/T/…
23 # Bug Report: https://lore.kernel.org/amd-gfx/[email protected]/T/…
Di915-cml-flakes.txt2 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
9 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
16 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
23 # Bug Report: https://lore.kernel.org/intel-gfx/[email protected]/…
/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Daspeed-gfx.txt1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
8 - compatible: "aspeed,ast2500-gfx", "syscon"
9 - reg: contains offset/length value of the GFX memory
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/linux-6.14.4/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu_v13_0_1_ppsmc.h55 #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
56 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
61 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
67 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
71 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
72 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
83 #define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number
/linux-6.14.4/drivers/pmdomain/qcom/
Drpmhpd.c110 static struct rpmhpd gfx = { variable
111 .pd = { .name = "gfx", },
112 .res_name = "gfx.lvl",
244 [SA8775P_GFX] = &gfx,
267 [RPMHPD_GFX] = &gfx,
290 [SDM670_GFX] = &gfx,
308 [SDM845_GFX] = &gfx,
366 [SM6350_GFX] = &gfx,
382 [RPMHPD_GFX] = &gfx,
400 [SM8150_GFX] = &gfx,
[all …]

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