Lines Matching full:gfx
889 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
890 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
891 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
892 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
936 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v7_0_init_microcode()
942 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v7_0_init_microcode()
954 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v7_0_init_microcode()
961 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, in gfx_v7_0_init_microcode()
968 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v7_0_init_microcode()
973 pr_err("gfx7: Failed to load firmware %s gfx firmware\n", chip_name); in gfx_v7_0_init_microcode()
993 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v7_0_tiling_mode_table_init()
995 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v7_0_tiling_mode_table_init()
999 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1000 macrotile = adev->gfx.config.macrotile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1002 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_tiling_mode_table_init()
1599 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()
1600 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1642 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1643 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v7_0_write_harvested_raster_configs()
1759 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()
1760 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1764 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1765 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1768 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1774 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v7_0_setup_rb()
1775 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v7_0_setup_rb()
1777 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()
1778 adev->gfx.config.max_shader_engines, 16); in gfx_v7_0_setup_rb()
1782 if (!adev->gfx.config.backend_enable_mask || in gfx_v7_0_setup_rb()
1783 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v7_0_setup_rb()
1788 adev->gfx.config.backend_enable_mask, in gfx_v7_0_setup_rb()
1793 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1794 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1796 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v7_0_setup_rb()
1798 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v7_0_setup_rb()
1800 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v7_0_setup_rb()
1802 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v7_0_setup_rb()
1862 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v7_0_init_gds_vmid()
1877 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v7_0_config_init()
1885 * init the gfx constants such as the 3D engine, tiling configuration
1896 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1897 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1898 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1982 …((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIF… in gfx_v7_0_constants_init()
1983 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v7_0_constants_init()
1984 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v7_0_constants_init()
1985 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v7_0_constants_init()
2021 * gfx_v7_0_ring_test_ring - basic gfx ring test
2025 * Allocate a scratch register and write to it using the gfx ring (CIK).
2026 * Provides a basic gfx ring test to verify that the ring is working.
2108 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2115 * Emits a fence sequence number on the gfx ring and flushes
2196 * on the gfx ring. IBs are usually generated by userspace
2199 * on the gfx ring for execution by the GPU.
2292 * Allocate an IB and execute it on the gfx ring (CIK).
2293 * Provides a basic gfx ring test to verify that IBs are working.
2340 * On CIK, gfx and compute now have independent command processors.
2342 * GFX
2343 * Gfx consists of a single ring and can process both gfx jobs and
2344 * compute jobs. The gfx CP consists of three microengines (ME):
2362 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2367 * Halts or unhalts the gfx MEs.
2381 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2385 * Loads the gfx PFP, ME, and CE ucode.
2396 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2399 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2400 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2401 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2406 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2407 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2408 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2409 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2410 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2411 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2417 (adev->gfx.pfp_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2423 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2427 (adev->gfx.ce_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2433 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2437 (adev->gfx.me_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2443 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2449 * gfx_v7_0_cp_gfx_start - start the gfx ring
2459 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2465 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v7_0_cp_gfx_start()
2477 /* init the CE partitions. CE only used for gfx on CIK */ in gfx_v7_0_cp_gfx_start()
2491 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
2505 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_cp_gfx_start()
2506 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_cp_gfx_start()
2525 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2529 * Program the location and size of the gfx ring buffer
2553 /* ring 0 - compute and gfx */ in gfx_v7_0_cp_gfx_resume()
2555 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2659 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
2662 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2664 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2665 adev->gfx.mec_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2672 (adev->gfx.mec_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2683 if (!adev->gfx.mec2_fw) in gfx_v7_0_cp_compute_load_microcode()
2686 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2688 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2689 adev->gfx.mec2_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2694 (adev->gfx.mec2_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2718 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
2719 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_fini()
2727 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v7_0_mec_fini()
2736 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v7_0_mec_init()
2742 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
2748 &adev->gfx.mec.hpd_eop_obj, in gfx_v7_0_mec_init()
2749 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v7_0_mec_init()
2760 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2761 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2771 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) in gfx_v7_0_compute_pipe_init()
2775 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; in gfx_v7_0_compute_pipe_init()
2970 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_queue_init()
3016 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
3017 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) in gfx_v7_0_cp_compute_resume()
3021 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3031 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3032 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_resume()
3204 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3205 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3208 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3209 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3213 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3214 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3215 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3217 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3218 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
3221 cs_data = adev->gfx.rlc.cs_data; in gfx_v7_0_rlc_init()
3237 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_rlc_init()
3244 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v7_0_rlc_init()
3245 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v7_0_rlc_init()
3268 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3269 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3420 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
3423 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v7_0_rlc_resume()
3425 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); in gfx_v7_0_rlc_resume()
3426 adev->gfx.rlc_feature_version = le32_to_cpu( in gfx_v7_0_rlc_resume()
3429 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_rlc_resume()
3435 adev->gfx.rlc.funcs->reset(adev); in gfx_v7_0_rlc_resume()
3453 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_rlc_resume()
3458 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v7_0_rlc_resume()
3466 adev->gfx.rlc.funcs->start(adev); in gfx_v7_0_rlc_resume()
3746 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()
3755 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v7_0_init_ao_cu_mask()
3759 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v7_0_init_ao_cu_mask()
3799 if (adev->gfx.rlc.cs_data) { in gfx_v7_0_init_gfx_cgpg()
3801 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3802 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3803 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
3809 if (adev->gfx.rlc.reg_list) { in gfx_v7_0_init_gfx_cgpg()
3811 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3812 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
3820 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3821 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3856 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_size()
3864 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_size()
3889 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_buffer()
3901 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_buffer()
3996 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4000 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4147 adev->gfx.xcc_mask = 1; in gfx_v7_0_early_init()
4148 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; in gfx_v7_0_early_init()
4149 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v7_0_early_init()
4151 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; in gfx_v7_0_early_init()
4152 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; in gfx_v7_0_early_init()
4165 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_late_init()
4169 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_late_init()
4185 adev->gfx.config.max_shader_engines = 2; in gfx_v7_0_gpu_early_init()
4186 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4187 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_early_init()
4188 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4189 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4190 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4191 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4192 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4193 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4195 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4196 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4197 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4198 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4202 adev->gfx.config.max_shader_engines = 4; in gfx_v7_0_gpu_early_init()
4203 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()
4204 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_early_init()
4205 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4206 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()
4207 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v7_0_gpu_early_init()
4208 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4209 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4210 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4212 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4213 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4214 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4215 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4219 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4220 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4221 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_early_init()
4222 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4223 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4224 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4225 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4226 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4227 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4229 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4230 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4231 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4232 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4238 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4239 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()
4240 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_early_init()
4241 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4242 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
4243 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v7_0_gpu_early_init()
4244 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4245 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4246 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4248 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4249 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4250 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4251 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4256 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4257 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v7_0_gpu_early_init()
4259 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v7_0_gpu_early_init()
4261 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v7_0_gpu_early_init()
4264 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
4265 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v7_0_gpu_early_init()
4289 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v7_0_gpu_early_init()
4291 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v7_0_gpu_early_init()
4294 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v7_0_gpu_early_init()
4295 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v7_0_gpu_early_init()
4296 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v7_0_gpu_early_init()
4299 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v7_0_gpu_early_init()
4300 adev->gfx.config.num_gpus = 1; in gfx_v7_0_gpu_early_init()
4301 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v7_0_gpu_early_init()
4305 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_gpu_early_init()
4317 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v7_0_gpu_early_init()
4325 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_ring_init()
4338 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v7_0_compute_ring_init()
4343 &adev->gfx.eop_irq, irq_type, in gfx_v7_0_compute_ring_init()
4360 adev->gfx.mec.num_mec = 2; in gfx_v7_0_sw_init()
4367 adev->gfx.mec.num_mec = 1; in gfx_v7_0_sw_init()
4370 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v7_0_sw_init()
4371 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v7_0_sw_init()
4374 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); in gfx_v7_0_sw_init()
4380 &adev->gfx.priv_reg_irq); in gfx_v7_0_sw_init()
4386 &adev->gfx.priv_inst_irq); in gfx_v7_0_sw_init()
4392 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v7_0_sw_init()
4396 r = adev->gfx.rlc.funcs->init(adev); in gfx_v7_0_sw_init()
4409 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4410 ring = &adev->gfx.gfx_ring[i]; in gfx_v7_0_sw_init()
4412 sprintf(ring->name, "gfx"); in gfx_v7_0_sw_init()
4414 &adev->gfx.eop_irq, in gfx_v7_0_sw_init()
4423 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
4424 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
4425 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v7_0_sw_init()
4441 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_sw_init()
4453 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4454 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v7_0_sw_fini()
4455 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4456 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v7_0_sw_fini()
4461 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v7_0_sw_fini()
4462 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
4463 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_sw_fini()
4464 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_sw_fini()
4465 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v7_0_sw_fini()
4466 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_sw_fini()
4467 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_sw_fini()
4482 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v7_0_hw_init()
4484 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v7_0_hw_init()
4499 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_hw_fini()
4500 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_hw_fini()
4502 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_hw_fini()
4583 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_soft_reset()
4585 /* Disable GFX parsing/prefetching */ in gfx_v7_0_soft_reset()
4798 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
4802 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
4803 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_eop_irq()
4823 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v7_0_fault()
4827 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()
4828 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_fault()
4850 // XXX soft reset the gfx block only in gfx_v7_0_priv_inst_irq()
4960 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v7_0_reset_kgq()
5087 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
5088 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; in gfx_v7_0_set_ring_funcs()
5089 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5090 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; in gfx_v7_0_set_ring_funcs()
5110 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v7_0_set_irq_funcs()
5111 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; in gfx_v7_0_set_irq_funcs()
5113 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5114 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; in gfx_v7_0_set_irq_funcs()
5116 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5117 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; in gfx_v7_0_set_irq_funcs()
5134 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v7_0_get_cu_info()
5141 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v7_0_get_cu_info()
5148 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5149 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5160 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v7_0_get_cu_info()