Lines Matching full:gfx
42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
218 /* gfx queue registers */
301 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
366 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
434 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
628 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
629 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
630 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
631 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
633 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
665 if ((adev->gfx.me_fw_version >= 1505) && in gfx_v11_0_check_fw_cp_gfx_shadow()
666 (adev->gfx.pfp_fw_version >= 1600) && in gfx_v11_0_check_fw_cp_gfx_shadow()
667 (adev->gfx.mec_fw_version >= 512)) { in gfx_v11_0_check_fw_cp_gfx_shadow()
669 adev->gfx.cp_gfx_shadow = true; in gfx_v11_0_check_fw_cp_gfx_shadow()
671 adev->gfx.cp_gfx_shadow = false; in gfx_v11_0_check_fw_cp_gfx_shadow()
675 adev->gfx.cp_gfx_shadow = false; in gfx_v11_0_check_fw_cp_gfx_shadow()
691 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v11_0_init_microcode()
697 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( in gfx_v11_0_init_microcode()
699 adev->gfx.pfp_fw->data, 2, 0); in gfx_v11_0_init_microcode()
700 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
709 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v11_0_init_microcode()
714 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
725 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v11_0_init_microcode()
729 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v11_0_init_microcode()
734 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_init_microcode()
742 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v11_0_init_microcode()
747 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
761 /* only one MEC for gfx 11.0.0. */ in gfx_v11_0_init_microcode()
762 adev->gfx.mec2_fw = NULL; in gfx_v11_0_init_microcode()
766 if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) { in gfx_v11_0_init_microcode()
767 err = adev->gfx.imu.funcs->init_microcode(adev); in gfx_v11_0_init_microcode()
775 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_init_microcode()
776 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_init_microcode()
777 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_init_microcode()
778 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_init_microcode()
822 if (adev->gfx.rlc.cs_data == NULL) in gfx_v11_0_get_csb_buffer()
834 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v11_0_get_csb_buffer()
853 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); in gfx_v11_0_get_csb_buffer()
865 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v11_0_rlc_fini()
866 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v11_0_rlc_fini()
867 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v11_0_rlc_fini()
870 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v11_0_rlc_fini()
871 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v11_0_rlc_fini()
872 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v11_0_rlc_fini()
879 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
887 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v11_0_init_rlcg_reg_access_ctrl()
895 adev->gfx.rlc.cs_data = gfx11_cs_data; in gfx_v11_0_rlc_init()
897 cs_data = adev->gfx.rlc.cs_data; in gfx_v11_0_rlc_init()
907 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v11_0_rlc_init()
908 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v11_0_rlc_init()
915 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v11_0_mec_fini()
916 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v11_0_mec_fini()
917 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); in gfx_v11_0_mec_fini()
922 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v11_0_me_init()
933 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v11_0_mec_init()
937 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; in gfx_v11_0_mec_init()
942 &adev->gfx.mec.hpd_eop_obj, in gfx_v11_0_mec_init()
943 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v11_0_mec_init()
953 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
954 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
1043 if (adev->gfx.cp_gfx_shadow) { in gfx_v11_0_get_gfx_shadow_info()
1071 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
1072 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1073 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1074 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1075 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1078 adev->gfx.ras = &gfx_v11_0_3_ras; in gfx_v11_0_gpu_early_init()
1079 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
1080 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1081 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1082 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1083 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1090 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
1091 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1092 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1093 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v11_0_gpu_early_init()
1094 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; in gfx_v11_0_gpu_early_init()
1111 ring = &adev->gfx.gfx_ring[ring_id]; in gfx_v11_0_gfx_ring_init()
1130 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v11_0_gfx_ring_init()
1142 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v11_0_compute_ring_init()
1152 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v11_0_compute_ring_init()
1158 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v11_0_compute_ring_init()
1163 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v11_0_compute_ring_init()
1219 &adev->gfx.rlc.rlc_autoload_bo, in gfx_v11_0_rlc_autoload_buffer_init()
1220 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v11_0_rlc_autoload_buffer_init()
1221 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v11_0_rlc_autoload_buffer_init()
1239 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1294 if (adev->gfx.rs64_enable) { in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1297 adev->gfx.pfp_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1299 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1305 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1314 adev->gfx.me_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1316 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1322 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1331 adev->gfx.mec_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1333 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1339 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1353 adev->gfx.pfp_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1354 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1362 adev->gfx.me_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1363 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1371 adev->gfx.mec_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1372 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1382 adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1383 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1393 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1395 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1401 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1486 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; in gfx_v11_0_rlc_backdoor_autoload_enable()
1494 if (adev->gfx.imu.funcs->load_microcode) in gfx_v11_0_rlc_backdoor_autoload_enable()
1495 adev->gfx.imu.funcs->load_microcode(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1497 if (adev->gfx.imu.funcs->setup_imu) in gfx_v11_0_rlc_backdoor_autoload_enable()
1498 adev->gfx.imu.funcs->setup_imu(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1499 if (adev->gfx.imu.funcs->start_imu) in gfx_v11_0_rlc_backdoor_autoload_enable()
1500 adev->gfx.imu.funcs->start_imu(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1516 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); in gfx_v11_0_alloc_ip_dump()
1517 adev->gfx.ip_dump_core = NULL; in gfx_v11_0_alloc_ip_dump()
1519 adev->gfx.ip_dump_core = ptr; in gfx_v11_0_alloc_ip_dump()
1524 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v11_0_alloc_ip_dump()
1525 adev->gfx.mec.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1530 adev->gfx.ip_dump_compute_queues = NULL; in gfx_v11_0_alloc_ip_dump()
1532 adev->gfx.ip_dump_compute_queues = ptr; in gfx_v11_0_alloc_ip_dump()
1535 /* Allocate memory for gfx queue registers for all the instances */ in gfx_v11_0_alloc_ip_dump()
1537 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * in gfx_v11_0_alloc_ip_dump()
1538 adev->gfx.me.num_queue_per_pipe; in gfx_v11_0_alloc_ip_dump()
1542 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); in gfx_v11_0_alloc_ip_dump()
1543 adev->gfx.ip_dump_gfx_queues = NULL; in gfx_v11_0_alloc_ip_dump()
1545 adev->gfx.ip_dump_gfx_queues = ptr; in gfx_v11_0_alloc_ip_dump()
1559 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1560 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1561 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1562 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1563 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1564 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1571 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1572 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1573 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1574 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1575 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1576 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1579 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1580 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1581 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1582 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1583 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1584 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v11_0_sw_init()
1592 adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; in gfx_v11_0_sw_init()
1593 adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); in gfx_v11_0_sw_init()
1594 if (adev->gfx.me_fw_version >= 2280 && in gfx_v11_0_sw_init()
1595 adev->gfx.pfp_fw_version >= 2370 && in gfx_v11_0_sw_init()
1596 adev->gfx.mec_fw_version >= 2450 && in gfx_v11_0_sw_init()
1598 adev->gfx.enable_cleaner_shader = true; in gfx_v11_0_sw_init()
1599 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); in gfx_v11_0_sw_init()
1601 adev->gfx.enable_cleaner_shader = false; in gfx_v11_0_sw_init()
1607 adev->gfx.enable_cleaner_shader = false; in gfx_v11_0_sw_init()
1619 &adev->gfx.eop_irq); in gfx_v11_0_sw_init()
1626 &adev->gfx.bad_op_irq); in gfx_v11_0_sw_init()
1633 &adev->gfx.priv_reg_irq); in gfx_v11_0_sw_init()
1640 &adev->gfx.priv_inst_irq); in gfx_v11_0_sw_init()
1647 &adev->gfx.rlc_gc_fed_irq); in gfx_v11_0_sw_init()
1651 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v11_0_sw_init()
1667 /* set up the gfx ring */ in gfx_v11_0_sw_init()
1668 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_sw_init()
1669 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1670 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
1685 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
1686 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1687 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_sw_init()
1702 adev->gfx.gfx_supported_reset = in gfx_v11_0_sw_init()
1703 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); in gfx_v11_0_sw_init()
1704 adev->gfx.compute_supported_reset = in gfx_v11_0_sw_init()
1705 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); in gfx_v11_0_sw_init()
1710 if ((adev->gfx.me_fw_version >= 2280) && in gfx_v11_0_sw_init()
1711 (adev->gfx.mec_fw_version >= 2410)) { in gfx_v11_0_sw_init()
1712 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in gfx_v11_0_sw_init()
1713 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in gfx_v11_0_sw_init()
1748 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); in gfx_v11_0_sw_init()
1763 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_pfp_fini()
1764 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_pfp_fini()
1765 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_pfp_fini()
1767 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, in gfx_v11_0_pfp_fini()
1768 &adev->gfx.pfp.pfp_fw_data_gpu_addr, in gfx_v11_0_pfp_fini()
1769 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); in gfx_v11_0_pfp_fini()
1774 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v11_0_me_fini()
1775 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_me_fini()
1776 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_me_fini()
1778 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, in gfx_v11_0_me_fini()
1779 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_me_fini()
1780 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_me_fini()
1785 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, in gfx_v11_0_rlc_autoload_buffer_fini()
1786 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v11_0_rlc_autoload_buffer_fini()
1787 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v11_0_rlc_autoload_buffer_fini()
1795 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_sw_fini()
1796 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v11_0_sw_fini()
1797 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()
1798 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v11_0_sw_fini()
1803 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v11_0_sw_fini()
1821 kfree(adev->gfx.ip_dump_core); in gfx_v11_0_sw_fini()
1822 kfree(adev->gfx.ip_dump_compute_queues); in gfx_v11_0_sw_fini()
1823 kfree(adev->gfx.ip_dump_gfx_queues); in gfx_v11_0_sw_fini()
1867 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
1868 adev->gfx.config.max_shader_engines); in gfx_v11_0_get_sa_active_bitmap()
1886 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * in gfx_v11_0_get_rb_active_bitmap()
1887 adev->gfx.config.max_shader_engines); in gfx_v11_0_get_rb_active_bitmap()
1908 max_sa = adev->gfx.config.max_shader_engines * in gfx_v11_0_setup_rb()
1909 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1910 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / in gfx_v11_0_setup_rb()
1911 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1920 adev->gfx.config.backend_enable_mask = active_rb_bitmap; in gfx_v11_0_setup_rb()
1921 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); in gfx_v11_0_setup_rb()
1975 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v11_0_init_gds_vmid()
1999 adev->gfx.config.tcc_disabled_mask = in gfx_v11_0_get_tcc_info()
2013 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v11_0_constants_init()
2015 adev->gfx.config.pa_sc_tile_steering_override = 0; in gfx_v11_0_constants_init()
2019 adev->gfx.config.ta_cntl2_truncate_coord_mode = in gfx_v11_0_constants_init()
2095 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_enable_gui_idle_interrupt()
2096 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_enable_gui_idle_interrupt()
2117 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v11_0_init_csb()
2120 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v11_0_init_csb()
2122 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v11_0_init_csb()
2123 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
2194 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlcg_microcode()
2195 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcg_microcode()
2206 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
2216 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlc_iram_dram_microcode()
2218 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlc_iram_dram_microcode()
2231 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2233 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlc_iram_dram_microcode()
2245 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2260 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlcp_rlcv_microcode()
2262 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcp_rlcv_microcode()
2275 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2281 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcp_rlcv_microcode()
2294 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2307 if (!adev->gfx.rlc_fw) in gfx_v11_0_rlc_load_microcode()
2310 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_load_microcode()
2346 adev->gfx.rlc.funcs->stop(adev); in gfx_v11_0_rlc_resume()
2363 adev->gfx.rlc.funcs->start(adev); in gfx_v11_0_rlc_resume()
2508 adev->gfx.pfp_fw->data; in gfx_v11_0_config_pfp_cache_rs64()
2558 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_pfp_cache_rs64()
2630 adev->gfx.me_fw->data; in gfx_v11_0_config_me_cache_rs64()
2681 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_me_cache_rs64()
2753 adev->gfx.mec_fw->data; in gfx_v11_0_config_mec_cache_rs64()
2767 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_config_mec_cache_rs64()
2836 adev->gfx.mec_fw->data; in gfx_v11_0_config_gfx_rs64()
2838 adev->gfx.me_fw->data; in gfx_v11_0_config_gfx_rs64()
2840 adev->gfx.pfp_fw->data; in gfx_v11_0_config_gfx_rs64()
2949 if (adev->gfx.rs64_enable) { in gfx_v11_0_wait_for_rlc_autoload_complete()
2950 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2952 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2957 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2959 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2964 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2966 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2972 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2977 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2982 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
3009 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); in gfx_v11_0_cp_gfx_enable()
3022 adev->gfx.pfp_fw->data; in gfx_v11_0_cp_gfx_load_pfp_microcode()
3026 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode()
3032 &adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode()
3033 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode()
3034 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3041 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3043 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3044 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3046 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3054 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3069 adev->gfx.pfp_fw->data; in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3074 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3078 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3087 &adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3088 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3089 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3100 &adev->gfx.pfp.pfp_fw_data_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3101 &adev->gfx.pfp.pfp_fw_data_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3102 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3109 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3110 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3112 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3113 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3114 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3115 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3121 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3123 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3168 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3199 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3201 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3240 adev->gfx.me_fw->data; in gfx_v11_0_cp_gfx_load_me_microcode()
3244 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode()
3250 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode()
3251 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode()
3252 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode()
3259 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v11_0_cp_gfx_load_me_microcode()
3261 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
3262 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
3264 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); in gfx_v11_0_cp_gfx_load_me_microcode()
3272 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
3287 adev->gfx.me_fw->data; in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3292 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3296 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3305 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3306 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3307 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3318 &adev->gfx.me.me_fw_data_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3319 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3320 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3327 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3328 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3330 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3331 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3332 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3333 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3339 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3341 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3387 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3418 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3420 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3455 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) in gfx_v11_0_cp_gfx_load_microcode()
3460 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_gfx_load_microcode()
3469 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_gfx_load_microcode()
3491 adev->gfx.config.max_hw_contexts - 1); in gfx_v11_0_cp_gfx_start()
3497 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_start()
3529 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); in gfx_v11_0_cp_gfx_start()
3540 if (adev->gfx.num_gfx_rings > 1) { in gfx_v11_0_cp_gfx_start()
3541 /* maximum supported gfx ring is 2 */ in gfx_v11_0_cp_gfx_start()
3542 ring = &adev->gfx.gfx_ring[1]; in gfx_v11_0_cp_gfx_start()
3606 /* Init gfx ring 0 for pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3611 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_resume()
3646 /* Init gfx ring 1 for pipe 1 */ in gfx_v11_0_cp_gfx_resume()
3647 if (adev->gfx.num_gfx_rings > 1) { in gfx_v11_0_cp_gfx_resume()
3650 /* maximum supported gfx ring is 2 */ in gfx_v11_0_cp_gfx_resume()
3651 ring = &adev->gfx.gfx_ring[1]; in gfx_v11_0_cp_gfx_resume()
3697 if (adev->gfx.rs64_enable) { in gfx_v11_0_cp_compute_enable()
3746 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode()
3751 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v11_0_cp_compute_load_microcode()
3755 (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode()
3761 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode()
3762 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode()
3772 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3773 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3775 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode()
3784 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3798 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode_rs64()
3803 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; in gfx_v11_0_cp_compute_load_microcode_rs64()
3806 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode_rs64()
3810 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode_rs64()
3818 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3819 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3831 &adev->gfx.mec.mec_fw_data_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3832 &adev->gfx.mec.mec_fw_data_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3843 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3844 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3845 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3846 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3860 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3863 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3865 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
3873 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3875 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
3974 /* set up gfx hqd wptr */ in gfx_v11_0_gfx_mqd_init()
3994 /* set up gfx queue priority */ in gfx_v11_0_gfx_mqd_init()
4002 /* set up gfx hqd base. this is similar as CP_RB_BASE */ in gfx_v11_0_gfx_mqd_init()
4053 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v11_0_kgq_init_queue()
4062 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_kgq_init_queue()
4063 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4066 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_kgq_init_queue()
4067 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4082 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_async_gfx_ring_resume()
4083 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_async_gfx_ring_resume()
4356 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4357 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4379 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4380 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4390 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v11_0_kcq_init_queue()
4400 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4401 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4404 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4405 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4420 ring = &adev->gfx.kiq[0].ring; in gfx_v11_0_kiq_resume()
4448 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()
4449 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_kcq_resume()
4484 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_resume()
4520 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_resume()
4521 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_resume()
4527 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()
4528 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_cp_resume()
4570 if (adev->gfx.rs64_enable) { in gfx_v11_0_select_cp_fw_arch()
4592 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()
4595 adev->gfx.config.gb_addr_config = gb_addr_config; in get_gb_addr_config()
4597 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()
4598 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4601 adev->gfx.config.max_tile_pipes = in get_gb_addr_config()
4602 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()
4604 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()
4605 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4607 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()
4608 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4610 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()
4611 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4613 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
4614 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4638 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, in gfx_v11_0_hw_init()
4639 adev->gfx.cleaner_shader_ptr); in gfx_v11_0_hw_init()
4642 if (adev->gfx.imu.funcs) { in gfx_v11_0_hw_init()
4644 if (adev->gfx.imu.funcs->program_rlc_ram) in gfx_v11_0_hw_init()
4645 adev->gfx.imu.funcs->program_rlc_ram(adev); in gfx_v11_0_hw_init()
4653 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { in gfx_v11_0_hw_init()
4654 if (adev->gfx.imu.funcs->load_microcode) in gfx_v11_0_hw_init()
4655 adev->gfx.imu.funcs->load_microcode(adev); in gfx_v11_0_hw_init()
4656 if (adev->gfx.imu.funcs->setup_imu) in gfx_v11_0_hw_init()
4657 adev->gfx.imu.funcs->setup_imu(adev); in gfx_v11_0_hw_init()
4658 if (adev->gfx.imu.funcs->start_imu) in gfx_v11_0_hw_init()
4659 adev->gfx.imu.funcs->start_imu(adev); in gfx_v11_0_hw_init()
4676 adev->gfx.is_poweron = true; in gfx_v11_0_hw_init()
4682 adev->gfx.rs64_enable) in gfx_v11_0_hw_init()
4695 * For gfx 11, rlc firmware loading relies on smu firmware is in gfx_v11_0_hw_init()
4727 if (!adev->gfx.imu_fw_version) in gfx_v11_0_hw_init()
4728 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); in gfx_v11_0_hw_init()
4737 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_hw_fini()
4738 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_hw_fini()
4739 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_hw_fini()
4766 adev->gfx.is_poweron = false; in gfx_v11_0_hw_fini()
4859 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
4860 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4861 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_soft_reset()
4869 for (i = 0; i < adev->gfx.me.num_me; ++i) { in gfx_v11_0_soft_reset()
4870 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4871 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
4881 /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ in gfx_v11_0_soft_reset()
4882 mutex_lock(&adev->gfx.reset_sem_mutex); in gfx_v11_0_soft_reset()
4885 mutex_unlock(&adev->gfx.reset_sem_mutex); in gfx_v11_0_soft_reset()
4886 DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); in gfx_v11_0_soft_reset()
4898 /* release the gfx mutex */ in gfx_v11_0_soft_reset()
4900 mutex_unlock(&adev->gfx.reset_sem_mutex); in gfx_v11_0_soft_reset()
4902 DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); in gfx_v11_0_soft_reset()
4980 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_check_soft_reset()
4981 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_check_soft_reset()
4987 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()
4988 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_check_soft_reset()
5001 * GFX soft reset will impact MES, need resume MES when do GFX soft reset in gfx_v11_0_post_soft_reset()
5013 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v11_0_get_gpu_clock_counter()
5019 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v11_0_get_gpu_clock_counter()
5068 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; in gfx_v11_0_early_init()
5070 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; in gfx_v11_0_early_init()
5071 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v11_0_early_init()
5092 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_late_init()
5096 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_late_init()
5100 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_late_init()
5686 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { in gfx_v11_0_ring_emit_ib_gfx()
5867 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v11_0_ring_emit_cntxcntl()
5901 if (!adev->gfx.cp_gfx_shadow || !ring->ring_obj) in gfx_v11_0_ring_emit_gfx_shadow()
5988 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v11_0_ring_preempt_ib()
6044 gfx[0].gfx_meta_data) + in gfx_v11_0_ring_emit_de_meta()
6052 gfx[0].gds_backup) + in gfx_v11_0_ring_emit_de_meta()
6329 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v11_0_eop_irq()
6331 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); in gfx_v11_0_eop_irq()
6335 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()
6336 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_eop_irq()
6364 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6365 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6377 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6378 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6410 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_bad_op_fault_state()
6411 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_bad_op_fault_state()
6423 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_bad_op_fault_state()
6424 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_bad_op_fault_state()
6455 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_inst_fault_state()
6456 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_inst_fault_state()
6489 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_handle_priv_fault()
6490 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_handle_priv_fault()
6498 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()
6499 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_handle_priv_fault()
6542 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) in gfx_v11_0_rlc_gc_fed_irq()
6543 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); in gfx_v11_0_rlc_gc_fed_irq()
6555 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6698 if (!adev->gfx.ip_dump_core) in gfx_v11_ip_print()
6704 adev->gfx.ip_dump_core[i]); in gfx_v11_ip_print()
6707 if (!adev->gfx.ip_dump_compute_queues) in gfx_v11_ip_print()
6712 adev->gfx.mec.num_mec, in gfx_v11_ip_print()
6713 adev->gfx.mec.num_pipe_per_mec, in gfx_v11_ip_print()
6714 adev->gfx.mec.num_queue_per_pipe); in gfx_v11_ip_print()
6716 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_print()
6717 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_print()
6718 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6723 adev->gfx.ip_dump_compute_queues[index + reg]); in gfx_v11_ip_print()
6730 /* print gfx queue registers for all instances */ in gfx_v11_ip_print()
6731 if (!adev->gfx.ip_dump_gfx_queues) in gfx_v11_ip_print()
6737 adev->gfx.me.num_me, in gfx_v11_ip_print()
6738 adev->gfx.me.num_pipe_per_me, in gfx_v11_ip_print()
6739 adev->gfx.me.num_queue_per_pipe); in gfx_v11_ip_print()
6741 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_print()
6742 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_print()
6743 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6748 adev->gfx.ip_dump_gfx_queues[index + reg]); in gfx_v11_ip_print()
6762 if (!adev->gfx.ip_dump_core) in gfx_v11_ip_dump()
6767 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i])); in gfx_v11_ip_dump()
6771 if (!adev->gfx.ip_dump_compute_queues) in gfx_v11_ip_dump()
6777 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_dump()
6778 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_dump()
6779 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6780 /* ME0 is for GFX so start from 1 for CP */ in gfx_v11_ip_dump()
6781 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); in gfx_v11_ip_dump()
6783 adev->gfx.ip_dump_compute_queues[index + reg] = in gfx_v11_ip_dump()
6795 /* dump gfx queue registers for all instances */ in gfx_v11_ip_dump()
6796 if (!adev->gfx.ip_dump_gfx_queues) in gfx_v11_ip_dump()
6803 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_dump()
6804 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_dump()
6805 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6809 adev->gfx.ip_dump_gfx_queues[index + reg] = in gfx_v11_ip_dump()
6982 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; in gfx_v11_0_set_ring_funcs()
6984 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_set_ring_funcs()
6985 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; in gfx_v11_0_set_ring_funcs()
6987 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
6988 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; in gfx_v11_0_set_ring_funcs()
7017 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v11_0_set_irq_funcs()
7018 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; in gfx_v11_0_set_irq_funcs()
7020 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v11_0_set_irq_funcs()
7021 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; in gfx_v11_0_set_irq_funcs()
7023 adev->gfx.bad_op_irq.num_types = 1; in gfx_v11_0_set_irq_funcs()
7024 adev->gfx.bad_op_irq.funcs = &gfx_v11_0_bad_op_irq_funcs; in gfx_v11_0_set_irq_funcs()
7026 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v11_0_set_irq_funcs()
7027 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; in gfx_v11_0_set_irq_funcs()
7029 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ in gfx_v11_0_set_irq_funcs()
7030 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; in gfx_v11_0_set_irq_funcs()
7037 adev->gfx.imu.mode = MISSION_MODE; in gfx_v11_0_set_imu_funcs()
7039 adev->gfx.imu.mode = DEBUG_MODE; in gfx_v11_0_set_imu_funcs()
7041 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; in gfx_v11_0_set_imu_funcs()
7046 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; in gfx_v11_0_set_rlc_funcs()
7051 unsigned total_cu = adev->gfx.config.max_cu_per_sh * in gfx_v11_0_set_gds_init()
7052 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
7053 adev->gfx.config.max_shader_engines; in gfx_v11_0_set_gds_init()
7063 /* set gfx eng mqd */ in gfx_v11_0_set_mqd_funcs()
7099 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7135 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v11_0_get_cu_info()
7136 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7137 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
7165 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v11_0_get_cu_info()