Lines Matching full:gfx
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
429 /* gfx queue registers */
3685 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx10_kiq_set_resources()
3808 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
4049 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
4050 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
4051 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
4052 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
4053 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
4054 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
4056 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
4061 adev->gfx.cp_fw_write_wait = false; in gfx_v10_0_check_fw_write_wait()
4069 if ((adev->gfx.me_fw_version >= 0x00000046) && in gfx_v10_0_check_fw_write_wait()
4070 (adev->gfx.me_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
4071 (adev->gfx.pfp_fw_version >= 0x00000068) && in gfx_v10_0_check_fw_write_wait()
4072 (adev->gfx.pfp_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
4073 (adev->gfx.mec_fw_version >= 0x0000005b) && in gfx_v10_0_check_fw_write_wait()
4074 (adev->gfx.mec_feature_version >= 27)) in gfx_v10_0_check_fw_write_wait()
4075 adev->gfx.cp_fw_write_wait = true; in gfx_v10_0_check_fw_write_wait()
4085 adev->gfx.cp_fw_write_wait = true; in gfx_v10_0_check_fw_write_wait()
4091 if (!adev->gfx.cp_fw_write_wait) in gfx_v10_0_check_fw_write_wait()
4141 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v10_0_init_microcode()
4148 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v10_0_init_microcode()
4155 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v10_0_init_microcode()
4164 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v10_0_init_microcode()
4171 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_microcode()
4179 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v10_0_init_microcode()
4187 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, in gfx_v10_0_init_microcode()
4195 adev->gfx.mec2_fw = NULL; in gfx_v10_0_init_microcode()
4201 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_init_microcode()
4202 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_init_microcode()
4203 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_init_microcode()
4204 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_init_microcode()
4205 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_init_microcode()
4206 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_init_microcode()
4252 if (adev->gfx.rlc.cs_data == NULL) in gfx_v10_0_get_csb_buffer()
4264 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v10_0_get_csb_buffer()
4283 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_get_csb_buffer()
4295 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v10_0_rlc_fini()
4296 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
4297 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v10_0_rlc_fini()
4300 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v10_0_rlc_fini()
4301 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v10_0_rlc_fini()
4302 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v10_0_rlc_fini()
4309 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4326 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4334 adev->gfx.rlc.cs_data = gfx10_cs_data; in gfx_v10_0_rlc_init()
4336 cs_data = adev->gfx.rlc.cs_data; in gfx_v10_0_rlc_init()
4350 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4351 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4356 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v10_0_me_init()
4372 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v10_0_mec_init()
4376 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; in gfx_v10_0_mec_init()
4381 &adev->gfx.mec.hpd_eop_obj, in gfx_v10_0_mec_init()
4382 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v10_0_mec_init()
4392 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4393 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4397 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_mec_init()
4399 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_mec_init()
4405 &adev->gfx.mec.mec_fw_obj, in gfx_v10_0_mec_init()
4406 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v10_0_mec_init()
4416 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4417 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4534 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4535 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4536 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4537 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v10_0_gpu_early_init()
4538 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4549 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4550 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4551 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4552 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v10_0_gpu_early_init()
4553 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4555 adev->gfx.config.gb_addr_config_fields.num_pkrs = in gfx_v10_0_gpu_early_init()
4560 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4561 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4562 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4563 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v10_0_gpu_early_init()
4564 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4572 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v10_0_gpu_early_init()
4574 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()
4575 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4578 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
4579 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()
4581 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()
4582 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4584 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()
4585 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4587 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()
4588 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4590 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()
4591 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4602 ring = &adev->gfx.gfx_ring[ring_id]; in gfx_v10_0_gfx_ring_init()
4621 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v10_0_gfx_ring_init()
4632 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v10_0_compute_ring_init()
4642 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v10_0_compute_ring_init()
4648 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v10_0_compute_ring_init()
4653 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v10_0_compute_ring_init()
4665 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); in gfx_v10_0_alloc_ip_dump()
4666 adev->gfx.ip_dump_core = NULL; in gfx_v10_0_alloc_ip_dump()
4668 adev->gfx.ip_dump_core = ptr; in gfx_v10_0_alloc_ip_dump()
4673 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v10_0_alloc_ip_dump()
4674 adev->gfx.mec.num_queue_per_pipe; in gfx_v10_0_alloc_ip_dump()
4679 adev->gfx.ip_dump_compute_queues = NULL; in gfx_v10_0_alloc_ip_dump()
4681 adev->gfx.ip_dump_compute_queues = ptr; in gfx_v10_0_alloc_ip_dump()
4684 /* Allocate memory for gfx queue registers for all the instances */ in gfx_v10_0_alloc_ip_dump()
4686 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * in gfx_v10_0_alloc_ip_dump()
4687 adev->gfx.me.num_queue_per_pipe; in gfx_v10_0_alloc_ip_dump()
4691 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); in gfx_v10_0_alloc_ip_dump()
4692 adev->gfx.ip_dump_gfx_queues = NULL; in gfx_v10_0_alloc_ip_dump()
4694 adev->gfx.ip_dump_gfx_queues = ptr; in gfx_v10_0_alloc_ip_dump()
4710 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4711 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4712 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4713 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4714 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4715 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4725 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4726 adev->gfx.me.num_pipe_per_me = 2; in gfx_v10_0_sw_init()
4727 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4728 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4729 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4730 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v10_0_sw_init()
4733 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4734 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4735 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4736 adev->gfx.mec.num_mec = 1; in gfx_v10_0_sw_init()
4737 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4738 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4746 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex; in gfx_v10_0_sw_init()
4747 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex); in gfx_v10_0_sw_init()
4748 if (adev->gfx.me_fw_version >= 64 && in gfx_v10_0_sw_init()
4749 adev->gfx.pfp_fw_version >= 100 && in gfx_v10_0_sw_init()
4750 adev->gfx.mec_fw_version >= 122) { in gfx_v10_0_sw_init()
4751 adev->gfx.enable_cleaner_shader = true; in gfx_v10_0_sw_init()
4752 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); in gfx_v10_0_sw_init()
4754 adev->gfx.enable_cleaner_shader = false; in gfx_v10_0_sw_init()
4760 adev->gfx.enable_cleaner_shader = false; in gfx_v10_0_sw_init()
4767 &adev->gfx.kiq[0].irq); in gfx_v10_0_sw_init()
4774 &adev->gfx.eop_irq); in gfx_v10_0_sw_init()
4781 &adev->gfx.bad_op_irq); in gfx_v10_0_sw_init()
4787 &adev->gfx.priv_reg_irq); in gfx_v10_0_sw_init()
4793 &adev->gfx.priv_inst_irq); in gfx_v10_0_sw_init()
4797 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v10_0_sw_init()
4801 if (adev->gfx.rlc.funcs) { in gfx_v10_0_sw_init()
4802 if (adev->gfx.rlc.funcs->init) { in gfx_v10_0_sw_init()
4803 r = adev->gfx.rlc.funcs->init(adev); in gfx_v10_0_sw_init()
4817 /* set up the gfx ring */ in gfx_v10_0_sw_init()
4818 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_sw_init()
4819 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
4820 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v10_0_sw_init()
4835 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v10_0_sw_init()
4836 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
4837 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v10_0_sw_init()
4852 adev->gfx.gfx_supported_reset = in gfx_v10_0_sw_init()
4853 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); in gfx_v10_0_sw_init()
4854 adev->gfx.compute_supported_reset = in gfx_v10_0_sw_init()
4855 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); in gfx_v10_0_sw_init()
4878 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; in gfx_v10_0_sw_init()
4893 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_pfp_fini()
4894 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_pfp_fini()
4895 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_pfp_fini()
4900 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, in gfx_v10_0_ce_fini()
4901 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_ce_fini()
4902 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_ce_fini()
4907 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v10_0_me_fini()
4908 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_me_fini()
4909 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_me_fini()
4917 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_sw_fini()
4918 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v10_0_sw_fini()
4919 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_sw_fini()
4920 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v10_0_sw_fini()
4924 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v10_0_sw_fini()
4941 kfree(adev->gfx.ip_dump_core); in gfx_v10_0_sw_fini()
4942 kfree(adev->gfx.ip_dump_compute_queues); in gfx_v10_0_sw_fini()
4943 kfree(adev->gfx.ip_dump_gfx_queues); in gfx_v10_0_sw_fini()
4985 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()
4986 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
4997 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
4998 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
5001 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_setup_rb()
5002 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
5003 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
5014 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
5021 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v10_0_setup_rb()
5022 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v10_0_setup_rb()
5034 /* for ASICs that integrates GFX v10.3 in gfx_v10_0_init_pa_sc_tile_steering_override()
5041 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
5042 adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
5046 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
5048 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; in gfx_v10_0_init_pa_sc_tile_steering_override()
5132 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v10_0_init_gds_vmid()
5149 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; in gfx_v10_0_tcp_harvest()
5174 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_tcp_harvest()
5175 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
5226 adev->gfx.config.tcc_disabled_mask = in gfx_v10_0_get_tcc_info()
5240 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v10_0_constants_init()
5242 adev->gfx.config.pa_sc_tile_steering_override = in gfx_v10_0_constants_init()
5319 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_enable_gui_idle_interrupt()
5320 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_enable_gui_idle_interrupt()
5341 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v10_0_init_csb()
5346 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5348 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5349 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5352 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5354 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5355 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5428 if (!adev->gfx.rlc_fw) in gfx_v10_0_rlc_load_microcode()
5431 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_load_microcode()
5434 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_load_microcode()
5445 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v10_0_rlc_load_microcode()
5473 adev->gfx.rlc.funcs->stop(adev); in gfx_v10_0_rlc_resume()
5497 adev->gfx.rlc.funcs->start(adev); in gfx_v10_0_rlc_resume()
5522 &adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_parse_rlc_toc()
5523 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_parse_rlc_toc()
5524 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_parse_rlc_toc()
5531 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); in gfx_v10_0_parse_rlc_toc()
5533 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_parse_rlc_toc()
5584 &adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5585 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5586 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5597 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5598 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5599 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5600 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5601 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5602 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5612 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; in gfx_v10_0_rlc_backdoor_autoload_copy_ucode()
5637 data = adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode()
5654 adev->gfx.pfp_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5655 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5664 adev->gfx.ce_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5665 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5674 adev->gfx.me_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5675 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5684 adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5685 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5694 adev->gfx.mec_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5695 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5751 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; in gfx_v10_0_rlc_backdoor_autoload_enable()
5800 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
5837 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
5874 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
5911 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
5988 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); in gfx_v10_0_cp_gfx_enable()
6003 adev->gfx.pfp_fw->data; in gfx_v10_0_cp_gfx_load_pfp_microcode()
6007 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_cp_gfx_load_pfp_microcode()
6013 &adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_cp_gfx_load_pfp_microcode()
6014 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_pfp_microcode()
6015 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6022 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6024 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6025 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6056 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6058 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6066 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6081 adev->gfx.ce_fw->data; in gfx_v10_0_cp_gfx_load_ce_microcode()
6085 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_cp_gfx_load_ce_microcode()
6091 &adev->gfx.ce.ce_fw_obj, in gfx_v10_0_cp_gfx_load_ce_microcode()
6092 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_ce_microcode()
6093 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_cp_gfx_load_ce_microcode()
6100 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_ce_microcode()
6102 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
6103 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
6133 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_ce_microcode()
6135 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_ce_microcode()
6143 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v10_0_cp_gfx_load_ce_microcode()
6158 adev->gfx.me_fw->data; in gfx_v10_0_cp_gfx_load_me_microcode()
6162 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_cp_gfx_load_me_microcode()
6168 &adev->gfx.me.me_fw_obj, in gfx_v10_0_cp_gfx_load_me_microcode()
6169 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_me_microcode()
6170 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_cp_gfx_load_me_microcode()
6177 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_me_microcode()
6179 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
6180 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
6210 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_me_microcode()
6212 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_me_microcode()
6220 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v10_0_cp_gfx_load_me_microcode()
6229 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v10_0_cp_gfx_load_microcode()
6265 adev->gfx.config.max_hw_contexts - 1); in gfx_v10_0_cp_gfx_start()
6270 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_start()
6302 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_cp_gfx_start()
6318 if (adev->gfx.num_gfx_rings > 1) { in gfx_v10_0_cp_gfx_start()
6319 /* maximum supported gfx ring is 2 */ in gfx_v10_0_cp_gfx_start()
6320 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_start()
6404 /* Init gfx ring 0 for pipe 0 */ in gfx_v10_0_cp_gfx_resume()
6409 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_resume()
6447 /* Init gfx ring 1 for pipe 1 */ in gfx_v10_0_cp_gfx_resume()
6448 if (adev->gfx.num_gfx_rings > 1) { in gfx_v10_0_cp_gfx_resume()
6451 /* maximum supported gfx ring is 2 */ in gfx_v10_0_cp_gfx_resume()
6452 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_resume()
6532 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v10_0_cp_compute_enable()
6545 if (!adev->gfx.mec_fw) in gfx_v10_0_cp_compute_load_microcode()
6550 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_cp_compute_load_microcode()
6554 (adev->gfx.mec_fw->data + in gfx_v10_0_cp_compute_load_microcode()
6585 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & in gfx_v10_0_cp_compute_load_microcode()
6588 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v10_0_cp_compute_load_microcode()
6597 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v10_0_cp_compute_load_microcode()
6662 /* set up gfx hqd wptr */ in gfx_v10_0_gfx_mqd_init()
6682 /* set up gfx queue priority */ in gfx_v10_0_gfx_mqd_init()
6690 /* set up gfx hqd base. this is similar as CP_RB_BASE */ in gfx_v10_0_gfx_mqd_init()
6741 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v10_0_kgq_init_queue()
6750 * if there are 2 gfx rings, set the lower doorbell in gfx_v10_0_kgq_init_queue()
6759 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v10_0_kgq_init_queue()
6760 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kgq_init_queue()
6770 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v10_0_kgq_init_queue()
6771 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kgq_init_queue()
6786 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_async_gfx_ring_resume()
6787 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_async_gfx_ring_resume()
7045 if (adev->gfx.kiq[0].mqd_backup) in gfx_v10_0_kiq_init_queue()
7046 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
7068 if (adev->gfx.kiq[0].mqd_backup) in gfx_v10_0_kiq_init_queue()
7069 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
7079 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v10_0_kcq_init_queue()
7089 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
7090 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
7093 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
7094 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
7109 ring = &adev->gfx.kiq[0].ring; in gfx_v10_0_kiq_resume()
7135 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_kcq_resume()
7136 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_kcq_resume()
7194 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_resume()
7195 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_resume()
7201 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_cp_resume()
7202 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_cp_resume()
7419 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, in gfx_v10_0_hw_init()
7420 adev->gfx.cleaner_shader_ptr); in gfx_v10_0_hw_init()
7424 * For gfx 10, rlc firmware loading relies on smu firmware is in gfx_v10_0_hw_init()
7470 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_hw_fini()
7471 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_hw_fini()
7472 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); in gfx_v10_0_hw_fini()
7494 * It causes GFX hang when another Win guest is rendering. in gfx_v10_0_hw_fini()
7599 /* Disable GFX parsing/prefetching */ in gfx_v10_0_soft_reset()
7730 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; in gfx_v10_0_early_init()
7738 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; in gfx_v10_0_early_init()
7748 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; in gfx_v10_0_early_init()
7754 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v10_0_early_init()
7775 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_late_init()
7779 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_late_init()
7783 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); in gfx_v10_0_late_init()
7890 /* MGLS is a global flag to control all MGLS in GFX */ in gfx_v10_0_update_medium_grain_clock_gating()
8196 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v10_0_update_gfx_clock_gating()
8213 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v10_0_update_gfx_clock_gating()
8592 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { in gfx_v10_0_ring_emit_ib_gfx()
8755 if (ring->adev->gfx.mcbp) in gfx_v10_0_ring_emit_cntxcntl()
8765 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v10_0_ring_emit_cntxcntl()
8805 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v10_0_ring_preempt_ib()
8977 fw_version_ok = adev->gfx.cp_fw_write_wait; in gfx_v10_0_ring_emit_reg_write_reg_wait()
9156 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v10_0_eop_irq()
9158 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); in gfx_v10_0_eop_irq()
9162 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_eop_irq()
9163 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_eop_irq()
9190 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_set_priv_reg_fault_state()
9191 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_priv_reg_fault_state()
9203 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_priv_reg_fault_state()
9204 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_0_set_priv_reg_fault_state()
9236 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_set_bad_op_fault_state()
9237 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_bad_op_fault_state()
9249 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_bad_op_fault_state()
9250 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_0_set_bad_op_fault_state()
9281 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_set_priv_inst_fault_state()
9282 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_priv_inst_fault_state()
9315 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_handle_priv_fault()
9316 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_handle_priv_fault()
9324 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_handle_priv_fault()
9325 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_handle_priv_fault()
9369 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); in gfx_v10_0_kiq_set_interrupt_state()
9413 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); in gfx_v10_0_kiq_irq()
9466 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v10_0_reset_kgq()
9534 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v10_0_reset_kcq()
9619 if (!adev->gfx.ip_dump_core) in gfx_v10_ip_print()
9625 adev->gfx.ip_dump_core[i]); in gfx_v10_ip_print()
9628 if (!adev->gfx.ip_dump_compute_queues) in gfx_v10_ip_print()
9633 adev->gfx.mec.num_mec, in gfx_v10_ip_print()
9634 adev->gfx.mec.num_pipe_per_mec, in gfx_v10_ip_print()
9635 adev->gfx.mec.num_queue_per_pipe); in gfx_v10_ip_print()
9637 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_print()
9638 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_ip_print()
9639 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v10_ip_print()
9644 adev->gfx.ip_dump_compute_queues[index + reg]); in gfx_v10_ip_print()
9651 /* print gfx queue registers for all instances */ in gfx_v10_ip_print()
9652 if (!adev->gfx.ip_dump_gfx_queues) in gfx_v10_ip_print()
9658 adev->gfx.me.num_me, in gfx_v10_ip_print()
9659 adev->gfx.me.num_pipe_per_me, in gfx_v10_ip_print()
9660 adev->gfx.me.num_queue_per_pipe); in gfx_v10_ip_print()
9662 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_ip_print()
9663 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_ip_print()
9664 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v10_ip_print()
9669 adev->gfx.ip_dump_gfx_queues[index + reg]); in gfx_v10_ip_print()
9683 if (!adev->gfx.ip_dump_core) in gfx_v10_ip_dump()
9688 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i])); in gfx_v10_ip_dump()
9692 if (!adev->gfx.ip_dump_compute_queues) in gfx_v10_ip_dump()
9698 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_dump()
9699 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v10_ip_dump()
9700 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v10_ip_dump()
9701 /* ME0 is for GFX so start from 1 for CP */ in gfx_v10_ip_dump()
9702 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); in gfx_v10_ip_dump()
9705 adev->gfx.ip_dump_compute_queues[index + reg] = in gfx_v10_ip_dump()
9717 /* dump gfx queue registers for all instances */ in gfx_v10_ip_dump()
9718 if (!adev->gfx.ip_dump_gfx_queues) in gfx_v10_ip_dump()
9725 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_ip_dump()
9726 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_ip_dump()
9727 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v10_ip_dump()
9731 adev->gfx.ip_dump_gfx_queues[index + reg] = in gfx_v10_ip_dump()
9904 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; in gfx_v10_0_set_ring_funcs()
9906 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_set_ring_funcs()
9907 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; in gfx_v10_0_set_ring_funcs()
9909 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_set_ring_funcs()
9910 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; in gfx_v10_0_set_ring_funcs()
9940 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
9941 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; in gfx_v10_0_set_irq_funcs()
9943 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
9944 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; in gfx_v10_0_set_irq_funcs()
9946 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
9947 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; in gfx_v10_0_set_irq_funcs()
9949 adev->gfx.bad_op_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
9950 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs; in gfx_v10_0_set_irq_funcs()
9952 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
9953 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; in gfx_v10_0_set_irq_funcs()
9970 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; in gfx_v10_0_set_rlc_funcs()
9974 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; in gfx_v10_0_set_rlc_funcs()
9983 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * in gfx_v10_0_set_gds_init()
9984 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
9985 adev->gfx.config.max_shader_engines; in gfx_v10_0_set_gds_init()
9995 /* set gfx eng mqd */ in gfx_v10_0_set_mqd_funcs()
10024 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v10_0_get_wgp_active_bitmap_per_sh()
10072 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_get_cu_info()
10073 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
10074 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
10095 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v10_0_get_cu_info()
10097 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v10_0_get_cu_info()
10131 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v10_3_get_disabled_sa()
10132 adev->gfx.config.max_shader_engines); in gfx_v10_3_get_disabled_sa()
10146 max_sa_per_se = adev->gfx.config.max_sh_per_se; in gfx_v10_3_program_pbb_mode()
10148 max_shader_engines = adev->gfx.config.max_shader_engines; in gfx_v10_3_program_pbb_mode()