Lines Matching full:gfx
339 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v6_0_init_microcode()
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
348 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v6_0_init_microcode()
353 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
354 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
355 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v6_0_init_microcode()
362 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
363 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
364 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
366 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v6_0_init_microcode()
371 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_init_microcode()
372 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
373 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
377 pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name); in gfx_v6_0_init_microcode()
378 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
379 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v6_0_init_microcode()
380 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v6_0_init_microcode()
381 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v6_0_init_microcode()
388 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v6_0_tiling_mode_table_init()
391 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); in gfx_v6_0_tiling_mode_table_init()
392 tilemode = adev->gfx.config.tile_mode_array; in gfx_v6_0_tiling_mode_table_init()
394 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v6_0_tiling_mode_table_init()
1324 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()
1325 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()
1366 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs()
1367 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v6_0_write_harvested_raster_configs()
1458 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v6_0_setup_rb()
1459 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()
1463 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1464 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1468 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()
1474 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v6_0_setup_rb()
1475 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v6_0_setup_rb()
1477 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v6_0_setup_rb()
1478 adev->gfx.config.max_shader_engines, 16); in gfx_v6_0_setup_rb()
1482 if (!adev->gfx.config.backend_enable_mask || in gfx_v6_0_setup_rb()
1483 adev->gfx.config.num_rbs >= num_rb_pipes) in gfx_v6_0_setup_rb()
1487 adev->gfx.config.backend_enable_mask, in gfx_v6_0_setup_rb()
1491 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1492 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1494 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v6_0_setup_rb()
1496 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v6_0_setup_rb()
1498 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v6_0_setup_rb()
1527 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v6_0_get_cu_enabled()
1539 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_spi()
1540 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1562 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v6_0_config_init()
1575 adev->gfx.config.max_shader_engines = 2; in gfx_v6_0_constants_init()
1576 adev->gfx.config.max_tile_pipes = 12; in gfx_v6_0_constants_init()
1577 adev->gfx.config.max_cu_per_sh = 8; in gfx_v6_0_constants_init()
1578 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1579 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1580 adev->gfx.config.max_texture_channel_caches = 12; in gfx_v6_0_constants_init()
1581 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1582 adev->gfx.config.max_gs_threads = 32; in gfx_v6_0_constants_init()
1583 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1585 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1586 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1587 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1588 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1592 adev->gfx.config.max_shader_engines = 2; in gfx_v6_0_constants_init()
1593 adev->gfx.config.max_tile_pipes = 8; in gfx_v6_0_constants_init()
1594 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()
1595 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1596 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1597 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v6_0_constants_init()
1598 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1599 adev->gfx.config.max_gs_threads = 32; in gfx_v6_0_constants_init()
1600 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1602 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1603 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1604 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1605 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1609 adev->gfx.config.max_shader_engines = 1; in gfx_v6_0_constants_init()
1610 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()
1611 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()
1612 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1613 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1614 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v6_0_constants_init()
1615 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1616 adev->gfx.config.max_gs_threads = 32; in gfx_v6_0_constants_init()
1617 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1619 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1620 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1621 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1622 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1626 adev->gfx.config.max_shader_engines = 1; in gfx_v6_0_constants_init()
1627 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()
1628 adev->gfx.config.max_cu_per_sh = 6; in gfx_v6_0_constants_init()
1629 adev->gfx.config.max_sh_per_se = 1; in gfx_v6_0_constants_init()
1630 adev->gfx.config.max_backends_per_se = 2; in gfx_v6_0_constants_init()
1631 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v6_0_constants_init()
1632 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1633 adev->gfx.config.max_gs_threads = 16; in gfx_v6_0_constants_init()
1634 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1636 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1637 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1638 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1639 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1643 adev->gfx.config.max_shader_engines = 1; in gfx_v6_0_constants_init()
1644 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()
1645 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()
1646 adev->gfx.config.max_sh_per_se = 1; in gfx_v6_0_constants_init()
1647 adev->gfx.config.max_backends_per_se = 1; in gfx_v6_0_constants_init()
1648 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v6_0_constants_init()
1649 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1650 adev->gfx.config.max_gs_threads = 16; in gfx_v6_0_constants_init()
1651 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1653 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1654 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1655 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1656 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1670 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v6_0_constants_init()
1671 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v6_0_constants_init()
1673 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
1674 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v6_0_constants_init()
1676 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v6_0_constants_init()
1677 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v6_0_constants_init()
1678 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v6_0_constants_init()
1679 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v6_0_constants_init()
1680 adev->gfx.config.num_gpus = 1; in gfx_v6_0_constants_init()
1681 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v6_0_constants_init()
1684 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v6_0_constants_init()
1697 if (adev->gfx.config.max_shader_engines == 2) in gfx_v6_0_constants_init()
1699 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v6_0_constants_init()
1734 …WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRO… in gfx_v6_0_constants_init()
1735 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v6_0_constants_init()
1736 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v6_0_constants_init()
1737 … (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v6_0_constants_init()
1872 * Allocate an IB and execute it on the gfx ring (SI).
1873 * Provides a basic gfx ring test to verify that IBs are working.
1940 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v6_0_cp_gfx_load_microcode()
1944 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_cp_gfx_load_microcode()
1945 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_cp_gfx_load_microcode()
1946 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_cp_gfx_load_microcode()
1954 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()
1963 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()
1972 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()
1990 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_start()
2001 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); in gfx_v6_0_cp_gfx_start()
2023 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2068 /* ring 0 - compute and gfx */ in gfx_v6_0_cp_gfx_resume()
2070 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_resume()
2114 if (ring == &adev->gfx.gfx_ring[0]) in gfx_v6_0_ring_get_wptr()
2116 else if (ring == &adev->gfx.compute_ring[0]) in gfx_v6_0_ring_get_wptr()
2118 else if (ring == &adev->gfx.compute_ring[1]) in gfx_v6_0_ring_get_wptr()
2136 if (ring == &adev->gfx.compute_ring[0]) { in gfx_v6_0_ring_set_wptr_compute()
2139 } else if (ring == &adev->gfx.compute_ring[1]) { in gfx_v6_0_ring_set_wptr_compute()
2159 ring = &adev->gfx.compute_ring[0]; in gfx_v6_0_cp_compute_resume()
2179 ring = &adev->gfx.compute_ring[1]; in gfx_v6_0_cp_compute_resume()
2200 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); in gfx_v6_0_cp_compute_resume()
2234 /* read a gfx register */ in gfx_v6_0_enable_gui_idle_interrupt()
2345 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2346 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2349 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2350 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2351 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2352 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
2363 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); in gfx_v6_0_rlc_init()
2364 dws = adev->gfx.rlc.clear_state_size + (256 / 4); in gfx_v6_0_rlc_init()
2369 &adev->gfx.rlc.clear_state_obj, in gfx_v6_0_rlc_init()
2370 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2371 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v6_0_rlc_init()
2379 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v6_0_rlc_init()
2380 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2383 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); in gfx_v6_0_rlc_init()
2385 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v6_0_rlc_init()
2386 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v6_0_rlc_init()
2492 if (!adev->gfx.rlc_fw) in gfx_v6_0_rlc_resume()
2495 adev->gfx.rlc.funcs->stop(adev); in gfx_v6_0_rlc_resume()
2496 adev->gfx.rlc.funcs->reset(adev); in gfx_v6_0_rlc_resume()
2510 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_rlc_resume()
2513 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_rlc_resume()
2524 adev->gfx.rlc.funcs->start(adev); in gfx_v6_0_rlc_resume()
2677 if (adev->gfx.rlc.cp_table_ptr == NULL)
2680 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2684 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2686 (adev->gfx.ce_fw->data +
2692 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2694 (adev->gfx.pfp_fw->data +
2700 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2702 (adev->gfx.me_fw->data +
2708 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2710 (adev->gfx.mec_fw->data +
2716 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2718 (adev->gfx.mec2_fw->data +
2750 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v6_0_init_ao_cu_mask()
2754 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v6_0_init_ao_cu_mask()
2790 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2792 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2814 if (adev->gfx.rlc.cs_data == NULL) in gfx_v6_0_get_csb_size()
2822 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_get_csb_size()
2847 if (adev->gfx.rlc.cs_data == NULL) in gfx_v6_0_get_csb_buffer()
2858 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_get_csb_buffer()
2874 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v6_0_get_csb_buffer()
2898 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_pg()
2899 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2906 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_pg()
2907 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2931 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v6_0_get_gpu_clock_counter()
2935 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v6_0_get_gpu_clock_counter()
3034 adev->gfx.xcc_mask = 1; in gfx_v6_0_early_init()
3035 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; in gfx_v6_0_early_init()
3036 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v6_0_early_init()
3038 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; in gfx_v6_0_early_init()
3039 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; in gfx_v6_0_early_init()
3052 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); in gfx_v6_0_sw_init()
3056 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); in gfx_v6_0_sw_init()
3060 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); in gfx_v6_0_sw_init()
3066 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v6_0_sw_init()
3070 r = adev->gfx.rlc.funcs->init(adev); in gfx_v6_0_sw_init()
3076 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v6_0_sw_init()
3077 ring = &adev->gfx.gfx_ring[i]; in gfx_v6_0_sw_init()
3079 sprintf(ring->name, "gfx"); in gfx_v6_0_sw_init()
3081 &adev->gfx.eop_irq, in gfx_v6_0_sw_init()
3088 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v6_0_sw_init()
3095 ring = &adev->gfx.compute_ring[i]; in gfx_v6_0_sw_init()
3105 &adev->gfx.eop_irq, irq_type, in gfx_v6_0_sw_init()
3119 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_sw_fini()
3120 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v6_0_sw_fini()
3121 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_sw_fini()
3122 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v6_0_sw_fini()
3136 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v6_0_hw_init()
3144 adev->gfx.ce_ram_size = 0x8000; in gfx_v6_0_hw_init()
3154 adev->gfx.rlc.funcs->stop(adev); in gfx_v6_0_hw_fini()
3331 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v6_0_eop_irq()
3335 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); in gfx_v6_0_eop_irq()
3350 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_fault()
3354 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; in gfx_v6_0_fault()
3511 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_set_ring_funcs()
3512 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; in gfx_v6_0_set_ring_funcs()
3513 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_set_ring_funcs()
3514 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; in gfx_v6_0_set_ring_funcs()
3534 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v6_0_set_irq_funcs()
3535 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; in gfx_v6_0_set_irq_funcs()
3537 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v6_0_set_irq_funcs()
3538 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; in gfx_v6_0_set_irq_funcs()
3540 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v6_0_set_irq_funcs()
3541 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; in gfx_v6_0_set_irq_funcs()
3548 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v6_0_get_cu_info()
3555 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v6_0_get_cu_info()
3562 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_get_cu_info()
3563 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_get_cu_info()
3574 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v6_0_get_cu_info()