Lines Matching full:gfx
46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
907 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx_v9_0_kiq_set_resources()
1066 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1256 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1257 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1258 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1259 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1260 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1261 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1263 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1268 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
1269 adev->gfx.mec_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
1273 ((adev->gfx.mec_fw_version < 0x000001a5) || in gfx_v9_0_check_fw_write_wait()
1274 (adev->gfx.mec_feature_version < 46) || in gfx_v9_0_check_fw_write_wait()
1275 (adev->gfx.pfp_fw_version < 0x000000b7) || in gfx_v9_0_check_fw_write_wait()
1276 (adev->gfx.pfp_feature_version < 46))) in gfx_v9_0_check_fw_write_wait()
1281 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1282 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
1283 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
1284 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1285 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1287 if ((adev->gfx.mec_fw_version >= 0x00000193) && in gfx_v9_0_check_fw_write_wait()
1288 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1289 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1292 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1293 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
1294 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
1295 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1296 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1298 if ((adev->gfx.mec_fw_version >= 0x00000196) && in gfx_v9_0_check_fw_write_wait()
1299 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1300 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1303 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1304 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
1305 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
1306 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1307 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1309 if ((adev->gfx.mec_fw_version >= 0x00000197) && in gfx_v9_0_check_fw_write_wait()
1310 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1311 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1315 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1316 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
1317 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
1318 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1319 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1321 if ((adev->gfx.mec_fw_version >= 0x00000192) && in gfx_v9_0_check_fw_write_wait()
1322 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1323 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1326 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1327 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1384 (adev->gfx.me_fw_version >= 0x000000a5) && in check_if_enlarge_doorbell_range()
1385 (adev->gfx.me_feature_version >= 52)) in check_if_enlarge_doorbell_range()
1406 adev->gfx.rlc_fw_version < 531) || in gfx_v9_0_check_if_need_gfxoff()
1407 (adev->gfx.rlc_feature_version < 1) || in gfx_v9_0_check_if_need_gfxoff()
1408 !adev->gfx.rlc.is_rlc_v2_1)) in gfx_v9_0_check_if_need_gfxoff()
1432 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v9_0_init_cp_gfx_microcode()
1439 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v9_0_init_cp_gfx_microcode()
1446 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v9_0_init_cp_gfx_microcode()
1455 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_init_cp_gfx_microcode()
1456 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_init_cp_gfx_microcode()
1457 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_init_cp_gfx_microcode()
1482 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v9_0_init_rlc_microcode()
1490 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v9_0_init_rlc_microcode()
1494 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v9_0_init_rlc_microcode()
1500 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_microcode()
1506 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_init_rlc_microcode()
1527 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v9_0_init_cp_compute_microcode()
1531 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v9_0_init_cp_compute_microcode()
1542 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, in gfx_v9_0_init_cp_compute_microcode()
1546 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, in gfx_v9_0_init_cp_compute_microcode()
1554 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_init_cp_compute_microcode()
1557 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; in gfx_v9_0_init_cp_compute_microcode()
1558 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; in gfx_v9_0_init_cp_compute_microcode()
1566 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_init_cp_compute_microcode()
1579 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_init_microcode()
1631 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_get_csb_buffer()
1643 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_get_csb_buffer()
1667 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v9_0_init_always_on_cu_mask()
1681 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_init_always_on_cu_mask()
1682 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
1688 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_init_always_on_cu_mask()
1824 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1832 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1840 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_rlc_init()
1842 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_rlc_init()
1853 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_rlc_init()
1864 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1865 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1879 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v9_0_mec_init()
1883 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()
1888 &adev->gfx.mec.hpd_eop_obj, in gfx_v9_0_mec_init()
1889 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v9_0_mec_init()
1899 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1900 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1903 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_mec_init()
1906 (adev->gfx.mec_fw->data + in gfx_v9_0_mec_init()
1912 &adev->gfx.mec.mec_fw_obj, in gfx_v9_0_mec_init()
1913 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v9_0_mec_init()
1923 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1924 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
2028 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2029 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2030 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2031 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2032 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2036 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2037 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2038 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2039 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2040 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2042 DRM_INFO("fix gfx.config for vega12\n"); in gfx_v9_0_gpu_early_init()
2045 adev->gfx.ras = &gfx_v9_0_ras; in gfx_v9_0_gpu_early_init()
2046 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2047 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2048 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2049 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2050 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2061 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2062 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2063 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2064 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2065 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2072 adev->gfx.ras = &gfx_v9_4_ras; in gfx_v9_0_gpu_early_init()
2073 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2074 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2075 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2076 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2077 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2083 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2084 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2085 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2086 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v9_0_gpu_early_init()
2087 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2093 adev->gfx.ras = &gfx_v9_4_2_ras; in gfx_v9_0_gpu_early_init()
2094 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2095 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2096 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2097 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2098 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2112 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v9_0_gpu_early_init()
2114 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()
2116 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2120 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
2121 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()
2123 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()
2125 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2128 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()
2130 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2133 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()
2135 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2138 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()
2140 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2143 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
2145 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2156 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
2159 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
2169 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v9_0_compute_ring_init()
2175 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v9_0_compute_ring_init()
2180 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v9_0_compute_ring_init()
2192 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); in gfx_v9_0_alloc_ip_dump()
2193 adev->gfx.ip_dump_core = NULL; in gfx_v9_0_alloc_ip_dump()
2195 adev->gfx.ip_dump_core = ptr; in gfx_v9_0_alloc_ip_dump()
2200 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_0_alloc_ip_dump()
2201 adev->gfx.mec.num_queue_per_pipe; in gfx_v9_0_alloc_ip_dump()
2206 adev->gfx.ip_dump_compute_queues = NULL; in gfx_v9_0_alloc_ip_dump()
2208 adev->gfx.ip_dump_compute_queues = ptr; in gfx_v9_0_alloc_ip_dump()
2229 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
2232 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
2238 adev->gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex; in gfx_v9_0_sw_init()
2239 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex); in gfx_v9_0_sw_init()
2240 if (adev->gfx.mec_fw_version >= 88) { in gfx_v9_0_sw_init()
2241 adev->gfx.enable_cleaner_shader = true; in gfx_v9_0_sw_init()
2242 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); in gfx_v9_0_sw_init()
2244 adev->gfx.enable_cleaner_shader = false; in gfx_v9_0_sw_init()
2250 adev->gfx.enable_cleaner_shader = false; in gfx_v9_0_sw_init()
2254 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v9_0_sw_init()
2255 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
2258 …_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); in gfx_v9_0_sw_init()
2265 &adev->gfx.bad_op_irq); in gfx_v9_0_sw_init()
2271 &adev->gfx.priv_reg_irq); in gfx_v9_0_sw_init()
2277 &adev->gfx.priv_inst_irq); in gfx_v9_0_sw_init()
2283 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2289 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2293 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v9_0_sw_init()
2295 if (adev->gfx.rlc.funcs) { in gfx_v9_0_sw_init()
2296 if (adev->gfx.rlc.funcs->init) { in gfx_v9_0_sw_init()
2297 r = adev->gfx.rlc.funcs->init(adev); in gfx_v9_0_sw_init()
2311 /* set up the gfx ring */ in gfx_v9_0_sw_init()
2312 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v9_0_sw_init()
2313 ring = &adev->gfx.gfx_ring[i]; in gfx_v9_0_sw_init()
2316 sprintf(ring->name, "gfx"); in gfx_v9_0_sw_init()
2323 ring->no_scheduler = adev->gfx.mcbp; in gfx_v9_0_sw_init()
2325 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v9_0_sw_init()
2333 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { in gfx_v9_0_sw_init()
2335 ring = &adev->gfx.sw_gfx_ring[i]; in gfx_v9_0_sw_init()
2343 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v9_0_sw_init()
2352 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], in gfx_v9_0_sw_init()
2359 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, in gfx_v9_0_sw_init()
2360 &adev->gfx.sw_gfx_ring[i]); in gfx_v9_0_sw_init()
2370 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
2371 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
2372 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_0_sw_init()
2389 adev->gfx.gfx_supported_reset = in gfx_v9_0_sw_init()
2390 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); in gfx_v9_0_sw_init()
2391 adev->gfx.compute_supported_reset = in gfx_v9_0_sw_init()
2392 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); in gfx_v9_0_sw_init()
2409 adev->gfx.ce_ram_size = 0x8000; in gfx_v9_0_sw_init()
2416 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); in gfx_v9_0_sw_init()
2435 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { in gfx_v9_0_sw_fini()
2437 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); in gfx_v9_0_sw_fini()
2438 amdgpu_ring_mux_fini(&adev->gfx.muxer); in gfx_v9_0_sw_fini()
2441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_sw_fini()
2442 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v9_0_sw_fini()
2443 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()
2444 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v9_0_sw_fini()
2447 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v9_0_sw_fini()
2453 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v9_0_sw_fini()
2454 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_sw_fini()
2455 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v9_0_sw_fini()
2457 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v9_0_sw_fini()
2458 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v9_0_sw_fini()
2459 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v9_0_sw_fini()
2465 kfree(adev->gfx.ip_dump_core); in gfx_v9_0_sw_fini()
2466 kfree(adev->gfx.ip_dump_compute_queues); in gfx_v9_0_sw_fini()
2510 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()
2511 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2521 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
2522 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2525 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_setup_rb()
2526 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2529 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2536 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v9_0_setup_rb()
2537 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v9_0_setup_rb()
2607 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v9_0_init_gds_vmid()
2645 if (adev->gfx.num_gfx_rings) in gfx_v9_0_constants_init()
2647 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v9_0_constants_init()
2648 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); in gfx_v9_0_constants_init()
2691 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_wait_for_rlc_serdes()
2692 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
2735 if (adev->gfx.num_gfx_rings) in gfx_v9_0_enable_gui_idle_interrupt()
2743 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v9_0_init_csb()
2746 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2748 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
2750 adev->gfx.rlc.clear_state_size); in gfx_v9_0_init_csb()
2803 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v9_1_init_rlc_save_restore_list()
2804 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v9_1_init_rlc_save_restore_list()
2811 adev->gfx.rlc.reg_list_format_direct_reg_list_length, in gfx_v9_1_init_rlc_save_restore_list()
2812 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v9_1_init_rlc_save_restore_list()
2827 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v9_1_init_rlc_save_restore_list()
2829 adev->gfx.rlc.register_restore[i]); in gfx_v9_1_init_rlc_save_restore_list()
2833 adev->gfx.rlc.reg_list_format_start); in gfx_v9_1_init_rlc_save_restore_list()
2836 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) in gfx_v9_1_init_rlc_save_restore_list()
2841 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { in gfx_v9_1_init_rlc_save_restore_list()
2863 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v9_1_init_rlc_save_restore_list()
2866 adev->gfx.rlc.reg_restore_list_size); in gfx_v9_1_init_rlc_save_restore_list()
2871 adev->gfx.rlc.starting_offsets_start); in gfx_v9_1_init_rlc_save_restore_list()
3034 /* read any GFX register to wake up GFX */ in gfx_v9_0_enable_gfx_pipeline_powergating()
3072 if (adev->gfx.rlc.is_rlc_v2_1) { in gfx_v9_0_init_pg()
3087 adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v9_0_init_pg()
3127 rlc_ucode_ver, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_start()
3145 if (!adev->gfx.rlc_fw) in gfx_v9_0_rlc_load_microcode()
3148 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_rlc_load_microcode()
3151 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v9_0_rlc_load_microcode()
3159 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_load_microcode()
3173 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_rlc_resume()
3209 adev->gfx.rlc.funcs->start(adev); in gfx_v9_0_rlc_resume()
3242 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
3246 adev->gfx.pfp_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3248 adev->gfx.ce_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3250 adev->gfx.me_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3260 (adev->gfx.pfp_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3266 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3270 (adev->gfx.ce_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3276 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3280 (adev->gfx.me_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3286 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3293 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_start()
3299 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v9_0_cp_gfx_start()
3375 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_resume()
3445 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v9_0_cp_compute_enable()
3457 if (!adev->gfx.mec_fw) in gfx_v9_0_cp_compute_load_microcode()
3462 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_cp_compute_load_microcode()
3466 (adev->gfx.mec_fw->data + in gfx_v9_0_cp_compute_load_microcode()
3474 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); in gfx_v9_0_cp_compute_load_microcode()
3476 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v9_0_cp_compute_load_microcode()
3486 adev->gfx.mec_fw_version); in gfx_v9_0_cp_compute_load_microcode()
3816 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup; in gfx_v9_0_kiq_init_queue()
3819 if (adev->gfx.kiq[0].mqd_backup) in gfx_v9_0_kiq_init_queue()
3820 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3844 if (adev->gfx.kiq[0].mqd_backup) in gfx_v9_0_kiq_init_queue()
3845 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3855 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v9_0_kcq_init_queue()
3861 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; in gfx_v9_0_kcq_init_queue()
3874 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3875 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3878 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3879 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3894 ring = &adev->gfx.kiq[0].ring; in gfx_v9_0_kiq_resume()
3920 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_resume()
3921 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kcq_resume()
3951 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_cp_resume()
3963 if (adev->gfx.num_gfx_rings) in gfx_v9_0_cp_resume()
3971 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_cp_resume()
3981 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_cp_resume()
3982 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_resume()
3988 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()
3989 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_cp_resume()
4018 if (adev->gfx.num_gfx_rings) in gfx_v9_0_cp_enable()
4028 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, in gfx_v9_0_hw_init()
4029 adev->gfx.cleaner_shader_ptr); in gfx_v9_0_hw_init()
4038 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v9_0_hw_init()
4057 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v9_0_hw_fini()
4058 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_hw_fini()
4059 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_hw_fini()
4060 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); in gfx_v9_0_hw_fini()
4083 soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, in gfx_v9_0_hw_fini()
4084 adev->gfx.kiq[0].ring.pipe, in gfx_v9_0_hw_fini()
4085 adev->gfx.kiq[0].ring.queue, 0, 0); in gfx_v9_0_hw_fini()
4086 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring); in gfx_v9_0_hw_fini()
4093 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ in gfx_v9_0_hw_fini()
4100 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_hw_fini()
4172 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_soft_reset()
4174 if (adev->gfx.num_gfx_rings) in gfx_v9_0_soft_reset()
4175 /* Disable GFX parsing/prefetching */ in gfx_v9_0_soft_reset()
4207 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v9_0_kiq_read_clock()
4297 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4307 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4581 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gds_workarounds()
4628 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gpr_workarounds()
4635 int compute_dim_x = adev->gfx.config.max_shader_engines * in gfx_v9_0_do_edc_gpr_workarounds()
4636 adev->gfx.config.max_cu_per_sh * in gfx_v9_0_do_edc_gpr_workarounds()
4637 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
4639 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; in gfx_v9_0_do_edc_gpr_workarounds()
4802 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; in gfx_v9_0_early_init()
4806 adev->gfx.num_gfx_rings = 0; in gfx_v9_0_early_init()
4808 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; in gfx_v9_0_early_init()
4809 adev->gfx.xcc_mask = 1; in gfx_v9_0_early_init()
4810 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v9_0_early_init()
4851 if (adev->gfx.ras && in gfx_v9_0_ecc_late_init()
4852 adev->gfx.ras->enable_watchdog_timer) in gfx_v9_0_ecc_late_init()
4853 adev->gfx.ras->enable_watchdog_timer(adev); in gfx_v9_0_ecc_late_init()
4863 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_late_init()
4867 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_late_init()
4871 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); in gfx_v9_0_late_init()
4986 /* MGLS is a global flag to control all MGLS in GFX */ in gfx_v9_0_update_medium_grain_clock_gating()
5039 if (!adev->gfx.num_gfx_rings) in gfx_v9_0_update_3d_clock_gating()
5142 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v9_0_update_gfx_clock_gating()
5151 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v9_0_update_gfx_clock_gating()
5260 /* update gfx cgpg state */ in gfx_v9_0_set_powergating_state()
5474 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_patch_ce_meta()
5506 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_patch_de_meta()
5705 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_emit_ce_meta()
5739 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v9_0_ring_preempt_ib()
5803 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_emit_de_meta()
5811 gfx[0].gds_backup) + in gfx_v9_0_ring_emit_de_meta()
5870 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v9_ring_emit_cntxcntl()
5957 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; in gfx_v9_0_ring_emit_reg_write_reg_wait()
6088 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_priv_reg_fault_state()
6089 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_0_set_priv_reg_fault_state()
6124 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_bad_op_fault_state()
6125 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_0_set_bad_op_fault_state()
6258 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_eop_irq()
6259 if (!adev->gfx.mcbp) { in gfx_v9_0_eop_irq()
6260 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v9_0_eop_irq()
6261 } else if (!amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { in gfx_v9_0_eop_irq()
6264 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); in gfx_v9_0_eop_irq()
6270 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_eop_irq()
6271 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_eop_irq()
6296 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v9_0_fault()
6300 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_fault()
6301 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_fault()
6797 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", in gfx_v9_0_ras_error_inject()
6805 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", in gfx_v9_0_ras_error_inject()
7011 dev_info(adev->dev, "GFX SubBlock %s, " in gfx_v9_0_ras_error_count()
7023 dev_info(adev->dev, "GFX SubBlock %s, " in gfx_v9_0_ras_error_count()
7188 * number of gfx waves. Setting 5 bit will make sure gfx only gets in gfx_v9_0_emit_wave_limit()
7201 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v9_0_emit_wave_limit()
7226 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v9_0_reset_kgq()
7272 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v9_0_reset_kcq()
7358 if (!adev->gfx.ip_dump_core) in gfx_v9_ip_print()
7364 adev->gfx.ip_dump_core[i]); in gfx_v9_ip_print()
7367 if (!adev->gfx.ip_dump_compute_queues) in gfx_v9_ip_print()
7372 adev->gfx.mec.num_mec, in gfx_v9_ip_print()
7373 adev->gfx.mec.num_pipe_per_mec, in gfx_v9_ip_print()
7374 adev->gfx.mec.num_queue_per_pipe); in gfx_v9_ip_print()
7376 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_print()
7377 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_ip_print()
7378 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_print()
7383 adev->gfx.ip_dump_compute_queues[index + reg]); in gfx_v9_ip_print()
7398 if (!adev->gfx.ip_dump_core || !adev->gfx.num_gfx_rings) in gfx_v9_ip_dump()
7403 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i])); in gfx_v9_ip_dump()
7407 if (!adev->gfx.ip_dump_compute_queues) in gfx_v9_ip_dump()
7413 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_dump()
7414 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v9_ip_dump()
7415 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v9_ip_dump()
7416 /* ME0 is for GFX so start from 1 for CP */ in gfx_v9_ip_dump()
7420 adev->gfx.ip_dump_compute_queues[index + reg] = in gfx_v9_ip_dump()
7450 * with compute and gfxoff and gfx pg. Disable gfx pg during in gfx_v9_0_ring_begin_use_compute()
7464 * with compute and gfxoff and gfx pg. Disable gfx pg during in gfx_v9_0_ring_end_use_compute()
7684 adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq; in gfx_v9_0_set_ring_funcs()
7686 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_set_ring_funcs()
7687 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; in gfx_v9_0_set_ring_funcs()
7689 if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { in gfx_v9_0_set_ring_funcs()
7691 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; in gfx_v9_0_set_ring_funcs()
7694 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_set_ring_funcs()
7695 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; in gfx_v9_0_set_ring_funcs()
7726 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
7727 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; in gfx_v9_0_set_irq_funcs()
7729 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
7730 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; in gfx_v9_0_set_irq_funcs()
7732 adev->gfx.bad_op_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
7733 adev->gfx.bad_op_irq.funcs = &gfx_v9_0_bad_op_irq_funcs; in gfx_v9_0_set_irq_funcs()
7735 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
7736 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; in gfx_v9_0_set_irq_funcs()
7738 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ in gfx_v9_0_set_irq_funcs()
7739 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; in gfx_v9_0_set_irq_funcs()
7753 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; in gfx_v9_0_set_rlc_funcs()
7841 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()
7859 if (adev->gfx.config.max_shader_engines * in gfx_v9_0_get_cu_info()
7860 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
7864 adev->gfx.config.max_shader_engines, in gfx_v9_0_get_cu_info()
7865 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
7868 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_get_cu_info()
7869 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
7875 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); in gfx_v9_0_get_cu_info()
7892 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_get_cu_info()
7894 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v9_0_get_cu_info()