Lines Matching full:gfx
927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
984 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
988 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
993 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, in gfx_v8_0_init_microcode()
999 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()
1000 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1001 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1004 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v8_0_init_microcode()
1008 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v8_0_init_microcode()
1013 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, in gfx_v8_0_init_microcode()
1019 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v8_0_init_microcode()
1020 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1022 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1025 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v8_0_init_microcode()
1029 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v8_0_init_microcode()
1034 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, in gfx_v8_0_init_microcode()
1040 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v8_0_init_microcode()
1041 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1042 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1048 if (adev->gfx.ce_feature_version >= 46 && in gfx_v8_0_init_microcode()
1049 adev->gfx.pfp_feature_version >= 46) { in gfx_v8_0_init_microcode()
1055 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, in gfx_v8_0_init_microcode()
1060 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()
1061 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1062 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1064 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1066 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1068 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1070 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1072 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1074 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1076 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1078 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1080 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
1083 adev->gfx.rlc.register_list_format = in gfx_v8_0_init_microcode()
1084 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v8_0_init_microcode()
1085 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v8_0_init_microcode()
1087 if (!adev->gfx.rlc.register_list_format) { in gfx_v8_0_init_microcode()
1094 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1095 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1097 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1101 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1102 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1105 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v8_0_init_microcode()
1109 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v8_0_init_microcode()
1114 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, in gfx_v8_0_init_microcode()
1120 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1121 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1122 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1127 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, in gfx_v8_0_init_microcode()
1131 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, in gfx_v8_0_init_microcode()
1136 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, in gfx_v8_0_init_microcode()
1142 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
1143 adev->gfx.mec2_fw_version = in gfx_v8_0_init_microcode()
1145 adev->gfx.mec2_feature_version = in gfx_v8_0_init_microcode()
1149 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1155 info->fw = adev->gfx.pfp_fw; in gfx_v8_0_init_microcode()
1162 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
1169 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
1176 info->fw = adev->gfx.rlc_fw; in gfx_v8_0_init_microcode()
1183 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1189 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1196 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1201 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1204 info->fw = adev->gfx.mec2_fw; in gfx_v8_0_init_microcode()
1212 dev_err(adev->dev, "gfx8: Failed to load firmware %s gfx firmware\n", chip_name); in gfx_v8_0_init_microcode()
1213 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1214 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1215 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1216 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1217 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1218 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1230 if (adev->gfx.rlc.cs_data == NULL) in gfx_v8_0_get_csb_buffer()
1242 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v8_0_get_csb_buffer()
1260 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1261 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1283 adev->gfx.rlc.cs_data = vi_cs_data; in gfx_v8_0_rlc_init()
1285 cs_data = adev->gfx.rlc.cs_data; in gfx_v8_0_rlc_init()
1296 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v8_0_rlc_init()
1303 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v8_0_rlc_init()
1304 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v8_0_rlc_init()
1311 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v8_0_mec_fini()
1320 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v8_0_mec_init()
1325 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()
1330 &adev->gfx.mec.hpd_eop_obj, in gfx_v8_0_mec_init()
1331 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v8_0_mec_init()
1340 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1341 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1503 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1675 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1676 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1677 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1678 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1679 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1680 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1681 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1682 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1683 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1685 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1686 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1687 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1688 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1692 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1693 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()
1694 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()
1695 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1696 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
1697 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v8_0_gpu_early_init()
1698 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1699 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1700 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1702 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1703 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1704 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1705 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1713 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1714 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1715 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1717 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1718 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1719 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1720 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1728 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1729 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1730 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1732 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1733 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1734 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1735 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1739 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1740 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()
1741 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1742 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1743 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1744 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v8_0_gpu_early_init()
1745 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1746 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1747 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1749 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1750 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1751 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1752 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1756 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1757 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1758 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1759 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1760 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1761 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1762 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1763 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1764 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1766 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1767 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1768 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1769 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1773 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1774 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1775 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1776 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1777 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()
1778 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1779 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1780 adev->gfx.config.max_gs_threads = 16; in gfx_v8_0_gpu_early_init()
1781 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1783 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1784 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1785 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1786 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1790 adev->gfx.config.max_shader_engines = 2; in gfx_v8_0_gpu_early_init()
1791 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()
1792 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1793 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1794 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1795 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v8_0_gpu_early_init()
1796 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1797 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1798 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1800 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1801 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1802 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1803 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1808 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1809 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v8_0_gpu_early_init()
1811 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1813 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1816 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1817 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v8_0_gpu_early_init()
1841 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v8_0_gpu_early_init()
1843 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v8_0_gpu_early_init()
1846 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v8_0_gpu_early_init()
1847 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v8_0_gpu_early_init()
1848 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v8_0_gpu_early_init()
1851 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v8_0_gpu_early_init()
1852 adev->gfx.config.num_gpus = 1; in gfx_v8_0_gpu_early_init()
1853 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v8_0_gpu_early_init()
1856 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_gpu_early_init()
1868 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v8_0_gpu_early_init()
1878 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1881 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1891 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v8_0_compute_ring_init()
1896 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v8_0_compute_ring_init()
1902 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v8_0_compute_ring_init()
1928 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1933 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
1937 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v8_0_sw_init()
1938 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
1941 …q_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); in gfx_v8_0_sw_init()
1947 &adev->gfx.priv_reg_irq); in gfx_v8_0_sw_init()
1953 &adev->gfx.priv_inst_irq); in gfx_v8_0_sw_init()
1959 &adev->gfx.cp_ecc_error_irq); in gfx_v8_0_sw_init()
1965 &adev->gfx.sq_irq); in gfx_v8_0_sw_init()
1971 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); in gfx_v8_0_sw_init()
1973 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v8_0_sw_init()
1977 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v8_0_sw_init()
1981 r = adev->gfx.rlc.funcs->init(adev); in gfx_v8_0_sw_init()
1993 /* set up the gfx ring */ in gfx_v8_0_sw_init()
1994 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
1995 ring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_sw_init()
1997 sprintf(ring->name, "gfx"); in gfx_v8_0_sw_init()
1998 /* no gfx doorbells on iceland */ in gfx_v8_0_sw_init()
2004 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v8_0_sw_init()
2014 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2015 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2016 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2047 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2061 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2062 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v8_0_sw_fini()
2063 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2064 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v8_0_sw_fini()
2067 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v8_0_sw_fini()
2072 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v8_0_sw_fini()
2073 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
2074 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_sw_fini()
2077 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v8_0_sw_fini()
2078 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_sw_fini()
2079 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_sw_fini()
2089 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2090 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2093 modearray = adev->gfx.config.tile_mode_array; in gfx_v8_0_tiling_mode_table_init()
2094 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
3448 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
3449 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3500 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3501 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs()
3610 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()
3611 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3615 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3616 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3619 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v8_0_setup_rb()
3625 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v8_0_setup_rb()
3626 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v8_0_setup_rb()
3628 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
3629 adev->gfx.config.max_shader_engines, 16); in gfx_v8_0_setup_rb()
3633 if (!adev->gfx.config.backend_enable_mask || in gfx_v8_0_setup_rb()
3634 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v8_0_setup_rb()
3639 adev->gfx.config.backend_enable_mask, in gfx_v8_0_setup_rb()
3644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3647 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v8_0_setup_rb()
3649 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v8_0_setup_rb()
3651 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v8_0_setup_rb()
3653 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v8_0_setup_rb()
3718 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v8_0_init_gds_vmid()
3735 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v8_0_config_init()
3739 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3750 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3751 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3752 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3807 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v8_0_constants_init()
3809 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v8_0_constants_init()
3811 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v8_0_constants_init()
3813 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v8_0_constants_init()
3833 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3834 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3880 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v8_0_init_csb()
3883 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3885 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3887 adev->gfx.rlc.clear_state_size); in gfx_v8_0_init_csb()
3950 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v8_0_init_save_restore_list()
3951 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v8_0_init_save_restore_list()
3957 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v8_0_init_save_restore_list()
3969 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3970 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()
3973 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); in gfx_v8_0_init_save_restore_list()
3974 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3977 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v8_0_init_save_restore_list()
3979 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); in gfx_v8_0_init_save_restore_list()
3984 adev->gfx.rlc.starting_offsets_start); in gfx_v8_0_init_save_restore_list()
4049 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v8_0_init_pg()
4051 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v8_0_init_pg()
4098 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_rlc_resume()
4099 adev->gfx.rlc.funcs->reset(adev); in gfx_v8_0_rlc_resume()
4101 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_rlc_resume()
4154 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4160 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v8_0_cp_gfx_start()
4196 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4197 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4218 /* no gfx doorbells on iceland */ in gfx_v8_0_set_cpg_door_bell()
4263 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4308 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4328 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kiq_kcq_enable()
4333 if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap)) in gfx_v8_0_kiq_kcq_enable()
4347 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()
4361 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4362 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_kcq_enable()
4614 if (adev->gfx.kiq[0].mqd_backup) in gfx_v8_0_kiq_init_queue()
4615 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4638 if (adev->gfx.kiq[0].mqd_backup) in gfx_v8_0_kiq_init_queue()
4639 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4649 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4661 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4662 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4665 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4666 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4689 ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kiq_resume()
4715 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()
4716 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_resume()
4747 /* collect all the ring_tests here, gfx, kiq, compute */ in gfx_v8_0_cp_test_all_rings()
4748 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_test_all_rings()
4753 ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_cp_test_all_rings()
4758 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()
4759 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_test_all_rings()
4808 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v8_0_hw_init()
4820 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kcq_disable()
4822 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v8_0_kcq_disable()
4826 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()
4827 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_disable()
4907 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
4908 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
4910 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
4912 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
4928 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_hw_fini()
4998 adev->gfx.grbm_soft_reset = grbm_soft_reset; in gfx_v8_0_check_soft_reset()
4999 adev->gfx.srbm_soft_reset = srbm_soft_reset; in gfx_v8_0_check_soft_reset()
5002 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5003 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5013 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_pre_soft_reset()
5014 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_pre_soft_reset()
5017 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_pre_soft_reset()
5020 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_pre_soft_reset()
5024 /* Disable GFX parsing/prefetching */ in gfx_v8_0_pre_soft_reset()
5033 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5034 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pre_soft_reset()
5055 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_soft_reset()
5056 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_soft_reset()
5059 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_soft_reset()
5060 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_soft_reset()
5116 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_post_soft_reset()
5117 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_post_soft_reset()
5120 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_post_soft_reset()
5128 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5129 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_post_soft_reset()
5147 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_post_soft_reset()
5164 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5168 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5283 adev->gfx.xcc_mask = 1; in gfx_v8_0_early_init()
5284 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; in gfx_v8_0_early_init()
5285 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v8_0_early_init()
5287 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; in gfx_v8_0_early_init()
5301 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5305 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5314 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5320 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
5366 /* Read any GFX register to wake up GFX. */ in cz_enable_gfx_pipeline_power_gating()
5786 /* disable cntx_empty_int_enable & GFX Idle interrupt */ in gfx_v8_0_update_coarse_grain_clock_gating()
5796 /* read gfx register to wake up cgcg */ in gfx_v8_0_update_coarse_grain_clock_gating()
6327 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v8_ring_emit_cntxcntl()
6648 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6652 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6653 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_eop_irq()
6678 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v8_0_fault()
6682 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()
6683 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_fault()
6792 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); in gfx_v8_0_sq_irq_work_func()
6809 if (work_pending(&adev->gfx.sq_work.work)) { in gfx_v8_0_sq_irq()
6812 adev->gfx.sq_work.ih_data = ih_data; in gfx_v8_0_sq_irq()
6813 schedule_work(&adev->gfx.sq_work.work); in gfx_v8_0_sq_irq()
6888 * number of gfx waves. Setting 5 bit will make sure gfx only gets in gfx_v8_0_emit_wave_limit()
6899 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v8_0_emit_wave_limit()
6910 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v8_0_reset_kgq()
7080 adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq; in gfx_v8_0_set_ring_funcs()
7082 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
7083 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; in gfx_v8_0_set_ring_funcs()
7085 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
7086 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; in gfx_v8_0_set_ring_funcs()
7116 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7117 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; in gfx_v8_0_set_irq_funcs()
7119 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7120 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; in gfx_v8_0_set_irq_funcs()
7122 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7123 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; in gfx_v8_0_set_irq_funcs()
7125 adev->gfx.cp_ecc_error_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7126 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; in gfx_v8_0_set_irq_funcs()
7128 adev->gfx.sq_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7129 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs; in gfx_v8_0_set_irq_funcs()
7134 adev->gfx.rlc.funcs = &iceland_rlc_funcs; in gfx_v8_0_set_rlc_funcs()
7167 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()
7176 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v8_0_get_cu_info()
7185 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()
7190 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7191 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7202 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()