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/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D10.3.3.rst65 - freedreno/ir3: fix FSLT/etc handling to return 0/-1 instead of 0/1.0
66 - freedreno/ir3: INEG operates on src0, not src1
67 - freedreno/ir3: add UARL support
68 - freedreno/ir3: negate result of USLT/etc
69 - freedreno/ir3: use unsigned comparison for UIF
70 - freedreno/ir3: add TXL support
71 - freedreno/ir3: fix UCMP handling
72 - freedreno/ir3: implement UMUL correctly
74 - freedreno/ir3: make texture instruction construction more dynamic
75 - freedreno/ir3: fix TXB/TXL to actually pull the bias/lod argument
[all …]
H A D20.2.0.rst142 - turnip/ir3: fine derivatives
185 - freedreno/ir3: allow copy-propagate from array
1020 - ir3: Unconditionally enable MERGEDREGS on a6xx
1140 - ir3: Fixup dual-source blending slot
1156 - ir3: Pass reserved_user_consts to ir3_shader_from_nir()
1158 - tu: Use the ir3 shader API
1161 - ir3: Don't calculate num_samp ourselves
1163 - ir3: Split out variant-specific lowering and optimizations
1164 - ir3, freedreno: Round up constlen earlier
1165 - ir3: Include ir3_compiler from ir3_shader
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H A D20.1.0.rst732 - nir: Move nir_lower_mediump_outputs from ir3
733 - ir3: Use shared mediump output lowering
964 - ir3: Disable copy prop for immediate ldlw offsets
1141 - tu: ir3: Emit push constants directly
1144 - ir3: Add bindless instruction encoding
1145 - ir3: Plumb through support for a1.x
1146 - ir3: Also don't propagate immediate offset with LDC
1147 - ir3: LDC also has a destination
1148 - ir3: Plumb through bindless support
1149 - ir3: Rewrite UBO push analysis to support bindless
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H A D21.2.0.rst1408 - ir3: Fix list corruption in legalize_block()
1409 - ir3: Reduce max const file indirect offset base to 9 bits
1410 - ir3, tu: Add compiler flag for robust UBO behavior
1415 - ir3/parser: Fix oob write with immediates array
1416 - ir3: Improve cat1 modifier disassembly
1417 - ir3: Assemble and disassemble swz/gat/sct
1418 - ir3: Prevent oob writes to inputs/outputs array
1420 - ir3, tu: Cleanup indirect i/o lowering
1425 - ir3/postsched: Fix dependencies for a0.x/p0.x
1426 - ir3/cp: Clone registers for compare-folding optimization
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H A D24.1.2.rst138 - ir3: fix crash in try_evict_regs with src reg
139 - ir3: fix handling of early clobbers in calc_min_limit_pressure
140 - ir3: set offset on splits created while spilling
141 - ir3: correctly set wrmask for reload.macro
142 - ir3: don't remove intervals for non-killed tex prefetch sources
143 - ir3: don't remove collects early while spilling
144 - ir3: expose instruction indexing helper for merge sets
145 - ir3: make indexing instructions optional in ir3_merge_regs
146 - ir3: index instructions before fixing up merge sets after spilling
147 - ir3: move liveness recalculation inside ir3_ra_shared
[all …]
H A D22.0.0.rst755 - ir3/cse: Support mov instructions
756 - ir3: Use stp/ldp base offset for {load,store}_scratch
762 - ir3: Emit barriers for images again
763 - ir3: Don't emit barriers for make_available/make_visible
764 - ir3/spill: Mark root as non-spillable after inserting
765 - ir3/spill: Initial implementation of rematerialization
771 - ir3/sched: Rewrite delay handling
772 - ir3/postsched: Fix copy-paste mistake
773 - ir3/postsched: Handle sync dependencies better
774 - ir3/delay: Ignore earlier definitions to the same register
[all …]
H A D24.2.0.rst735 - ir3: Add scan_clusters_macro to ir3_valid_flags()
736 - ir3: Add scan_clusters.macro to is_subgroup_cond_mov_macro()
737 - ir3: Validate tied sources better
738 - ir3/ra: Don't demote movmsk instructions to non-shared
739 - ir3: Rewrite postsched dependency handling
740 - ir3/legalize: Use define for register size
741 - ir3: Rewrite regmask implementation
742 - ir3/ra: Prepare for shared half-regs
743 - ir3/ra: Fix printing shared reg file
744 - ir3/ra: Prepare for shared phis
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H A D19.3.0.rst305 - freedreno/ir3: Link directly to Sethi-Ullman paper
1082 - freedreno/ir3: Add a NIR pass to select tex instructions eligible for
1085 - freedreno/ir3: Handle newly added opcode nir_op_imad24_ir3
1641 - freedreno/ir3: Add data structures to support texture pre-fetch
1642 - freedreno/ir3: Add support for texture sampling pre-dispatch
1643 - freedreno/ir3: fix printing output registers of FS.
1889 - freedreno/ir3: remove input ncomp field
1890 - freedreno/ir3: increase size of inputs/outputs arrays
1891 - freedreno/ir3: implement fdd{x,y}_coarse opcodes
1892 - freedreno/ir3: fix GETLOD for negative LODs
[all …]
H A D20.0.0.rst1048 - turnip: Drop redefinition of VALIDREG now that it's in ir3.h.
1096 - freedreno/ir3: Plumb the ir3_shader_variant into legalize.
1384 - freedreno/ir3: cleanup by removing repeated code
1386 - freedreno/ir3: fix printing output registers of FS.
1387 - freedreno/ir3: fixup when changing to mad.f16
1388 - freedreno/ir3: enable half precision for pre-fs texture fetch
1390 - freedreno/ir3: put the conversion back for half const to the right
1780 - freedreno/ir3: disable texture prefetch for 1d array textures
1813 - freedreno/ir3: add GLSL_SAMPLER_DIM_SUBPASS to tex_info
1838 - freedreno/ir3: lower mul_2x32_64
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H A D21.3.0.rst848 - freedreno/isa: generate ir3-isa.h
879 - ir3: Preserve gl_ViewportIndex in the binning shader
881 - ir3: Delete old packed struct encoding
886 - tu, freedreno/a6xx, ir3: Rewrite tess PrimID handling
888 - ir3: Document RA-related register flags better
899 - ir3: Add pass to remove unreachable blocks
900 - ir3/ra: Remove logical_unreachable
901 - ir3: Copy-propagate single-source phis
902 - ir3: Print physical successors/predecessors
903 - ir3/print: Use mesa_stream_log_printf for (kill)
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H A D19.1.0.rst578 - mesa: android: freedreno: build libfreedreno_{drm,ir3} static libs
1291 - nir: Add ir3-specific version of most SSBO intrinsics
1292 - ir3/nir: Add a new pass 'ir3_nir_lower_io_offsets'
1293 - ir3/compiler: Enable lower_io_offsets pass and handle new SSBO
1295 - ir3/lower_io_offsets: Try propagate SSBO's SHR into a previous shift
2329 - freedreno/ir3: fix input ncomp for vertex shaders
2483 - freedreno/ir3: use nir_src_as_uint in a few places
3444 - freedreno/ir3: Track whether shader needs derivatives
3445 - freedreno/ir3: Fix operand order for DSX/DSY
3447 - freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
[all …]
H A D21.0.0.rst761 - ir3: use intrinsic builders
783 - ir3: Expand cat6 a6xx opcode field
784 - ir3: Add more a6xx-specific cat6 opcodes
785 - ir3: Support assembling & disassembling getspid/getwid
786 - ir3: Fix STP/LDP assembly
787 - ir3/parser: Fix st{l,lw,g,p} and ld{l,lw,g,p} assembly
788 - ir3: Initial support for private memory
789 - ir3: Properly validate cat6 half-ness
793 - ir3: Enable nir_lower_vars_to_scratch on a6xx
794 - ir3/ra: Fix array reg liveness in scalar pass
[all …]
H A D21.1.0.rst1146 - freedreno/ir3: Use gl_varying_slot_name_for_stage()
1276 - freedreno/ir3: Handle sized tex destination types
1298 - ir3: Assume that nir_tex_instr::dest_type is sized
1302 - ir3/parser: Fix parsing of "0.0" in @const line
1304 - ir3/parser: Support labels
1305 - ir3/parser: Add ability to specify branchstack
1312 - ir3: Calcuate max_waves and threadsize
1313 - turnip: Use threadsize calculated by ir3
1314 - freedreno: Use threadsize calculated by ir3
1315 - freedreno/computerator: Use threadsize calculated by ir3
[all …]
H A D22.1.0.rst538 - ir3: set local_size for shaders of MESA_SHADER_KERNEL type
732 - ir3/spill: Fix simplify_phi_nodes with multiple loop nesting
736 - ir3: Use CAN_REORDER instead of NON_WRITEABLE
739 - ir3: Don't always set bindless_tex with readonly images
740 - ir3/nir: Fix 1d array readonly images
742 - ir3: Use isam for bindless images
743 - ir3/cp_postsched: Support multiple destinations
744 - ir3/dce: Support multiple destinations
745 - ir3/sched: Support multiple destinations
746 - ir3/ra: Fix tied destination handling with multiple destinations
[all …]
H A D10.5.1.rst117 - freedreno/ir3: fix array count returned by TXQ
118 - freedreno/ir3: get the # of miplevels from getinfo
180 - freedreno/ir3: fix silly typo for binning pass shaders
187 - freedreno/ir3: fix up cat6 instruction encodings
188 - freedreno/ir3: add support for memory (cat6) instructions
189 - freedreno/ir3: handle flat bypass for a4xx
190 - freedreno/ir3: fix failed assert in grouping
H A D24.1.0.rst1340 - ir3/ra: Add specialized shared register RA/spilling
1341 - ir3: Set branchstack earlier
1342 - ir3: Rewrite (jp) and branchstack handling
1343 - ir3: Calculate physical edges correctly
1344 - ir3: Fix comment thinko
1345 - ir3/ra: Fix bug with collect source handling
1347 - ir3/a7xx: Fix load_global_ir3 with immediate offset
1348 - ir3: Initial support for pushing globals with ldg.k
1372 - nir/divergence_analysis: Add ir3-specific intrinsics
1375 - ir3: Allow single-predecessor phis
[all …]
H A D22.2.0.rst168 - ir3: Infinite loop in scheduler when splitting
1227 - ir3: fix mem_ctx for ir3_disasm_info::nir
1243 - ir3: update ir3_const_state comment
1244 - ir3: copy req_local_mem for MESA_SHADER_KERNEL
1245 - ir3: fix output_loc size
1246 - ir3: remove unused patch_vertices_in
1247 - ir3: increment constoff right after it is assigned
1248 - ir3: fix tess param allocation
1249 - ir3: set UL flag before ir3_lower_subgroups
1279 - ir3: fix predicate splitting in scheduler
[all …]
/aosp_15_r20/external/mesa3d/src/freedreno/isa/
H A Dmeson.build5 'ir3-common.xml',
6 'ir3-cat0.xml',
7 'ir3-cat1.xml',
8 'ir3-cat2.xml',
9 'ir3-cat3.xml',
10 'ir3-cat4.xml',
11 'ir3-cat5.xml',
12 'ir3-cat6.xml',
13 'ir3-cat7.xml',
18 'ir3-isa',
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H A Dir3.xml48 <import file="ir3-common.xml"/>
52 Encoding of an ir3 instruction. All instructions are 64b.
81 <import file="ir3-cat0.xml"/>
82 <import file="ir3-cat1.xml"/>
83 <import file="ir3-cat2.xml"/>
84 <import file="ir3-cat3.xml"/>
85 <import file="ir3-cat4.xml"/>
86 <import file="ir3-cat5.xml"/>
87 <import file="ir3-cat6.xml"/>
88 <import file="ir3-cat7.xml"/>
H A Dencode.c9 #include "ir3/ir3.h"
10 #include "ir3/ir3_shader.h"
11 #include "ir3/instr-a3xx.h" // TODO move opc's and other useful things to ir3-instr.h or so
295 struct ir3 *shader = v->ir; in isa_assemble()
/aosp_15_r20/external/mesa3d/src/freedreno/ir3/
H A Dir3.h26 struct ir3;
31 void *data; /* used internally in ir3 assembler */
572 struct ir3 { struct
649 struct ir3_array *ir3_lookup_array(struct ir3 *ir, unsigned id);
653 struct ir3 *shader;
742 ir3_start_block(struct ir3 *ir) in ir3_start_block()
748 ir3_end_block(struct ir3 *ir) in ir3_end_block()
763 ir3_after_preamble(struct ir3 *ir) in ir3_after_preamble()
783 void ir3_calc_dominance(struct ir3 *ir);
788 struct ir3 *ir3_create(struct ir3_compiler *compiler,
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H A Dir3.c6 #include "ir3.h"
27 ir3_alloc(struct ir3 *shader, int sz) in ir3_alloc()
32 struct ir3 *
35 struct ir3 *shader = rzalloc(v, struct ir3); in ir3_create()
47 ir3_destroy(struct ir3 *shader) in ir3_destroy()
247 struct ir3 *shader = v->ir; in ir3_collect_info()
458 reg_create(struct ir3 *shader, int num, int flags) in reg_create()
470 struct ir3 *shader = instr->block->shader; in insert_instr()
494 ir3_block_create(struct ir3 *shader) in ir3_block_create()
640 struct ir3 *ir = instr->block->shader; in add_to_address_users()
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H A Dir3_ra.h10 #include "ir3.h"
141 struct ir3_liveness *ir3_calc_liveness_for(void *mem_ctx, struct ir3 *ir,
146 ir3_calc_liveness(void *mem_ctx, struct ir3 *ir) in ir3_calc_liveness()
154 void ir3_create_parallel_copies(struct ir3 *ir);
156 void ir3_merge_regs(struct ir3_liveness *live, struct ir3 *ir);
161 void ir3_index_instrs_for_merge_sets(struct ir3 *ir);
170 bool ir3_spill(struct ir3 *ir, struct ir3_shader_variant *v,
174 bool ir3_lower_spill(struct ir3 *ir);
/aosp_15_r20/external/mesa3d/src/gallium/drivers/freedreno/
H A Dmeson.build201 'ir3/ir3_cache.c',
202 'ir3/ir3_cache.h',
203 'ir3/ir3_const.h',
204 'ir3/ir3_descriptor.c',
205 'ir3/ir3_descriptor.h',
206 'ir3/ir3_gallium.c',
207 'ir3/ir3_gallium.h',
228 inc_freedreno, include_directories('ir3'),
312 ['ir3/ir3_cmdline.c', freedreno_xml_header_files],
/aosp_15_r20/external/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_cmdline.c23 #include "ir3/instr-a3xx.h"
24 #include "ir3/ir3.h"
25 #include "ir3/ir3_compiler.h"
26 #include "ir3/ir3_gallium.h"
27 #include "ir3/ir3_nir.h"

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