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/nrf52832-nimble/rt-thread/libcpu/arm/s3c24x0/
H A Ds3c24x0.h25 // Memory control
27 #define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
28 #define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
30 #define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
31 #define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
32 #define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
33 #define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
34 #define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
46 #define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
47 #define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
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H A Dmmu.c54 /* read control register */ in mmu_enable()
59 /* write back to control register */ in mmu_enable()
67 /* read control register */ in mmu_disable()
72 /* write back to control register */ in mmu_disable()
80 /* read control register */ in mmu_enable_icache()
85 /* write back to control register */ in mmu_enable_icache()
93 /* read control register */ in mmu_enable_dcache()
98 /* write back to control register */ in mmu_enable_dcache()
106 /* read control register */ in mmu_disable_icache()
111 /* write back to control register */ in mmu_disable_icache()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/include/controller/
H A Dble_ll_ctrl.h28 * LL control procedures. This "enumeration" is not in the specification;
29 * It is used to determine which LL control procedure is currently running
45 /* Checks if a particular control procedure is running */
49 /* LL control procedure timeout */
89 /* Maximum # of payload bytes in a LL control PDU */
93 /* LL control connection update request */
105 /* LL control channel map request */
114 * LL control terminate ind
119 /* LL control enc req */
130 /* LL control enc rsp */
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/nrf52832-nimble/rt-thread/components/CMSIS/Include/
H A Dcore_cmFunc.h58 /** \brief Get Control Register
60 This function returns the content of the Control Register.
62 \return Control Register value
66 register uint32_t __regControl __ASM("control"); in __get_CONTROL()
71 /** \brief Set Control Register
73 This function writes the given value to the Control Register.
75 \param [in] control Control Register value to set
77 __STATIC_INLINE void __set_CONTROL(uint32_t control) in __set_CONTROL() argument
79 register uint32_t __regControl __ASM("control"); in __set_CONTROL()
80 __regControl = control; in __set_CONTROL()
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H A Dcore_sc000.h194 \defgroup CMSIS_CORE Status and Control Registers
261 /** \brief Union type to access the Control Registers (CONTROL).
304 \defgroup CMSIS_SCB System Control Block (SCB)
305 \brief Type definitions for the System Control Block Registers
309 /** \brief Structure type to access the System Control Block (SCB).
314 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
316 … /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
317 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register …
318 …__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register …
321 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State …
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/nrf52832-nimble/rt-thread/components/net/uip/uip/
H A Dpt.h74 * \param pt A pointer to the protothread control structure.
111 * \param pt A pointer to the protothread control structure.
123 * \param pt A pointer to the protothread control structure.
143 * \param pt A pointer to the protothread control structure.
162 * \param pt A pointer to the protothread control structure.
185 * \param pt A pointer to the protothread control structure.
200 * \param pt A pointer to the protothread control structure.
201 * \param child A pointer to the child protothread's control structure.
225 * \param pt A pointer to the protothread control structure.
242 * \param pt A pointer to the protothread control structure.
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/nrf52832-nimble/rt-thread/libcpu/arm/armv6/
H A Dmmu.c258 /* read control register */ in mmu_enable()
267 /* write back to control register */ in mmu_enable()
275 /* read control register */ in mmu_disable()
280 /* write back to control register */ in mmu_disable()
288 /* read control register */ in mmu_enable_icache()
293 /* write back to control register */ in mmu_enable_icache()
301 /* read control register */ in mmu_enable_dcache()
306 /* write back to control register */ in mmu_enable_dcache()
314 /* read control register */ in mmu_disable_icache()
319 /* write back to control register */ in mmu_disable_icache()
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/nrf52832-nimble/rt-thread/libcpu/arm/dm36x/
H A Dmmu.c258 /* read control register */ in mmu_enable()
267 /* write back to control register */ in mmu_enable()
275 /* read control register */ in mmu_disable()
280 /* write back to control register */ in mmu_disable()
288 /* read control register */ in mmu_enable_icache()
293 /* write back to control register */ in mmu_enable_icache()
301 /* read control register */ in mmu_enable_dcache()
306 /* write back to control register */ in mmu_enable_dcache()
314 /* read control register */ in mmu_disable_icache()
319 /* write back to control register */ in mmu_disable_icache()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/src/
H A Dble_ll_ctrl.c50 * 2) Should we create pool of control pdu's?. Dont need more
61 * 8) How to count control pdus sent. DO we count enqueued + sent, or only
66 * XXX: I definitely have an issue with control procedures and connection
76 * This array contains the length of the CtrData field in LL control PDU's.
78 * control PDU, so total data channel payload length for the control pdu is
112 * Called to determine if a LL control procedure with an instant has
216 * Process a received LL_PING_RSP control pdu.
226 /* Stop the control procedure */ in ble_ll_ctrl_rx_ping_rsp()
360 * Called to make a connection update request LL control PDU
445 * Called to process and UNKNOWN_RSP LL control packet.
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/nrf52832-nimble/rt-thread/components/net/lwip-2.0.2/src/include/netif/ppp/
H A Dpppol2tp.h58 /* Mandatory bits for control: Control, Length, Sequence, Version 2 */
60 /* Forbidden bits for control: Offset, Priority */
74 /* Control Connection Management */
75 #define PPPOL2TP_MESSAGETYPE_SCCRQ 1 /* Start Control Connection Request */
76 #define PPPOL2TP_MESSAGETYPE_SCCRP 2 /* Start Control Connection Reply */
77 #define PPPOL2TP_MESSAGETYPE_SCCCN 3 /* Start Control Connection Connected */
78 #define PPPOL2TP_MESSAGETYPE_STOPCCN 4 /* Stop Control Connection Notification */
90 /* PPP Session Control */
95 #define PPPOL2TP_RESULTCODE 1 /* General request to clear control connection */
161 * PPPoL2TP interface control block.
/nrf52832-nimble/rt-thread/components/net/lwip-2.1.0/src/include/netif/ppp/
H A Dpppol2tp.h62 /* Mandatory bits for control: Control, Length, Sequence, Version 2 */
64 /* Forbidden bits for control: Offset, Priority */
78 /* Control Connection Management */
79 #define PPPOL2TP_MESSAGETYPE_SCCRQ 1 /* Start Control Connection Request */
80 #define PPPOL2TP_MESSAGETYPE_SCCRP 2 /* Start Control Connection Reply */
81 #define PPPOL2TP_MESSAGETYPE_SCCCN 3 /* Start Control Connection Connected */
82 #define PPPOL2TP_MESSAGETYPE_STOPCCN 4 /* Stop Control Connection Notification */
94 /* PPP Session Control */
99 #define PPPOL2TP_RESULTCODE 1 /* General request to clear control connection */
165 * PPPoL2TP interface control block.
/nrf52832-nimble/rt-thread/components/lwp/arch/arm/cortex-m4/
H A Dlwp_rvds.S35 MRS R2, CONTROL
37 MSR CONTROL, R2
95 MRS R3, CONTROL
98 MSR CONTROL, R3
123 MRS R2, CONTROL
125 MSR CONTROL, R2
H A Dlwp_iar.S34 MRS R2, CONTROL
36 MSR CONTROL, R2
90 MRS R3, CONTROL
93 MSR CONTROL, R3
115 MRS R2, CONTROL
117 MSR CONTROL, R2
H A Dlwp_gcc.S36 MRS R2, CONTROL
38 MSR CONTROL, R2
93 MRS R3, CONTROL
96 MSR CONTROL, R3
118 MRS R2, CONTROL
120 MSR CONTROL, R2
/nrf52832-nimble/rt-thread/components/lwp/arch/arm/cortex-m3/
H A Dlwp_iar.S34 MRS R2, CONTROL
36 MSR CONTROL, R2
90 MRS R3, CONTROL
93 MSR CONTROL, R3
115 MRS R2, CONTROL
117 MSR CONTROL, R2
H A Dlwp_rvds.S35 MRS R2, CONTROL
37 MSR CONTROL, R2
95 MRS R3, CONTROL
98 MSR CONTROL, R3
123 MRS R2, CONTROL
125 MSR CONTROL, R2
H A Dlwp_gcc.S36 MRS R2, CONTROL
38 MSR CONTROL, R2
93 MRS R3, CONTROL
96 MSR CONTROL, R3
118 MRS R2, CONTROL
120 MSR CONTROL, R2
/nrf52832-nimble/rt-thread/components/lwp/arch/arm/cortex-m7/
H A Dlwp_iar.S34 MRS R2, CONTROL
36 MSR CONTROL, R2
90 MRS R3, CONTROL
93 MSR CONTROL, R3
115 MRS R2, CONTROL
117 MSR CONTROL, R2
H A Dlwp_rvds.S35 MRS R2, CONTROL
37 MSR CONTROL, R2
95 MRS R3, CONTROL
98 MSR CONTROL, R3
123 MRS R2, CONTROL
125 MSR CONTROL, R2
H A Dlwp_gcc.S36 MRS R2, CONTROL
38 MSR CONTROL, R2
93 MRS R3, CONTROL
96 MSR CONTROL, R3
118 MRS R2, CONTROL
120 MSR CONTROL, R2
/nrf52832-nimble/rt-thread/components/drivers/misc/
H A Drt_drv_pwm.c20 if (pwm->ops->control) in _pwm_control()
22 result = pwm->ops->control(pwm, cmd, args); in _pwm_control()
43 if (pwm->ops->control) in _pwm_read()
45 result = pwm->ops->control(pwm, PWM_CMD_GET, &configuration); in _pwm_read()
71 if (pwm->ops->control) in _pwm_write()
73 result = pwm->ops->control(pwm, PWM_CMD_GET, &configuration); in _pwm_write()
81 result = pwm->ops->control(pwm, PWM_CMD_SET, &configuration); in _pwm_write()
117 device->parent.control = _pwm_control; in rt_device_pwm_register()
/nrf52832-nimble/nordic/cmsis/include/
H A Dcore_sc000.h245 \defgroup CMSIS_CORE Status and Control Registers
338 \brief Union type to access the Control Registers (CONTROL).
351 /* CONTROL Register Definitions */
352 …Pos 1U /*!< CONTROL: SPSEL Position */
353 …SEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
387 \defgroup CMSIS_SCB System Control Block (SCB)
388 \brief Type definitions for the System Control Block Registers
393 \brief Structure type to access the System Control Block (SCB).
398 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
400 …RCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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/nrf52832-nimble/rt-thread/components/net/lwip-2.1.0/src/netif/ppp/
H A Dppp.c384 * Release the control block.
638 * Create a new PPP control block.
640 * This initializes the PPP control block but does not
643 * Return a new PPP connection control block pointer
1493 { 0x4001, "Cray Communications Control Protocol" },
1504 { 0x8021, "Internet Protocol Control Protocol" },
1505 { 0x8023, "OSI Network Layer Control Protocol" },
1506 { 0x8025, "Xerox NS IDP Control Protocol" },
1507 { 0x8027, "DECnet Phase IV Control Protocol" },
1508 { 0x8029, "Appletalk Control Protocol" },
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/nrf52832-nimble/rt-thread/components/net/lwip-2.0.2/src/netif/ppp/
H A Dppp.c375 * Release the control block.
634 * Create a new PPP control block.
636 * This initializes the PPP control block but does not
639 * Return a new PPP connection control block pointer
1512 { 0x4001, "Cray Communications Control Protocol" },
1523 { 0x8021, "Internet Protocol Control Protocol" },
1524 { 0x8023, "OSI Network Layer Control Protocol" },
1525 { 0x8025, "Xerox NS IDP Control Protocol" },
1526 { 0x8027, "DECnet Phase IV Control Protocol" },
1527 { 0x8029, "Appletalk Control Protocol" },
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/nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/include/asm/
H A Dprocessor.h63 /* Floating Point Status and Control Register (FPSCR) Fields */
91 #define FPSCR_RN 0x00000003 /* FPU rounding control */
104 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
131 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
165 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
167 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
170 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
173 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
302 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
316 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
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