Lines Matching full:control
25 // Memory control
27 #define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
28 #define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
30 #define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
31 #define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
32 #define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
33 #define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
34 #define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
46 #define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
47 #define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
48 #define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
57 #define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
59 #define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
60 #define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
67 #define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
69 #define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
70 #define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
77 #define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
79 #define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
80 #define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
87 #define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
89 #define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
90 #define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
99 #define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control
100 #define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control
101 #define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
102 #define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
103 #define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
104 #define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
108 #define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1
109 #define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2
110 #define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3
111 #define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4
112 #define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5
124 #define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control
140 #define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control
141 #define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control
142 #define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control
143 #define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
144 #define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
151 #define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control
152 #define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control
153 #define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control
154 #define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
155 #define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
162 #define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control
163 #define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control
164 #define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control
165 #define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
166 #define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
209 #define TCON (*(volatile unsigned *)0x51000008) //Timer control
227 #define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
228 #define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
229 #define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
245 #define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
247 #define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
256 #define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
262 #define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
268 #define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
274 #define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
293 #define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
295 #define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
304 #define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
310 #define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
316 #define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
322 #define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
338 #define IICCON (*(volatile unsigned *)0x54000000) //IIC control
345 #define IISCON (*(volatile unsigned *)0x55000000) //IIS Control
348 #define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control
360 #define GPACON (*(volatile unsigned *)0x56000000) //Port A control
363 #define GPBCON (*(volatile unsigned *)0x56000010) //Port B control
365 #define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
367 #define GPCCON (*(volatile unsigned *)0x56000020) //Port C control
369 #define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
371 #define GPDCON (*(volatile unsigned *)0x56000030) //Port D control
373 #define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
375 #define GPECON (*(volatile unsigned *)0x56000040) //Port E control
377 #define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
379 #define GPFCON (*(volatile unsigned *)0x56000050) //Port F control
381 #define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
383 #define GPGCON (*(volatile unsigned *)0x56000060) //Port G control
385 #define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
387 #define GPHCON (*(volatile unsigned *)0x56000070) //Port H control
389 #define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
391 #define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control
393 #define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
395 #define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
396 #define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
397 #define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0
398 #define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1
399 #define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2
402 #define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2
403 #define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3
415 #define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control
417 #define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
434 #define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control
436 #define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
455 #define ADCCON (*(volatile unsigned *)0x58000000) //ADC control
456 #define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control
462 #define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
464 #define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
469 #define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
471 #define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
478 #define SDICON (*(volatile unsigned *)0x5a000000) //SDI control
481 #define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
489 #define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control