Lines Matching full:control
63 /* Floating Point Status and Control Register (FPSCR) Fields */
91 #define FPSCR_RN 0x00000003 /* FPU rounding control */
104 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
131 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
165 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
167 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
170 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
173 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
302 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
316 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
317 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
320 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
321 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
323 #define SPRN_MMUCR 0x3b2 /* MMU Control Register */
379 #define SPRN_TCR 0x3DA /* Timer Control Register */
381 #define SPRN_TCR 0x154 /* Book E Timer Control Register */
388 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
427 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
428 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
451 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
477 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
481 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
485 #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
486 #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
499 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
503 #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
517 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
521 #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
571 #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
572 #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
606 #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
607 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
641 #define TCR SPRN_TCR /* Timer Control Register */
719 /* Device Control Registers */
736 #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
737 #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
738 #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
739 #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */