| #
c90e3eac |
| 26-Jan-2024 |
Ziyue Zhang <[email protected]> |
rv64v: fix uop spilt and mask generate for vlm
|
| #
520f7dac |
| 22-Nov-2023 |
sinsanction <[email protected]> |
Backend: reduce imm width and move imm generating of instr fusion to enq
|
| #
395c8649 |
| 04-Jan-2024 |
Ziyue-Zhang <[email protected]> |
rv64v: add f2v to remove all fs1 duplicate logic (#2613)
* rv64v: add f2v to remove all fs1 duplicate logic
* rv64v: use IntFPToVec module for i2v and f2v
|
| #
b1712600 |
| 05-Dec-2023 |
Ziyue Zhang <[email protected]> |
rv64v: support copy data directly use i2v
* also fix some bugs for vwadd.w and vrgather.vi
|
| #
4cdab2a9 |
| 05-Dec-2023 |
Xuan Hu <[email protected]> |
decode: fix uops of vset
|
| #
e25c13fa |
| 23-Nov-2023 |
Xuan Hu <[email protected]> |
decode: refactor decode stage
* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in
decode: refactor decode stage
* The first complex inst can be send into DecodeComp if it is empty.
* VType in VTypeGen will be updated when vset inst entering DecodeComp.
* If there are left uops in decodeComp, the count of rename ready uops will be send to rename stage.
show more ...
|
| #
92c6b7ed |
| 08-Nov-2023 |
zhanglinjuan <[email protected]> |
Mgu: use sew as element width instead of eew for indexed loads/stores
|
| #
c379dcbe |
| 26-Oct-2023 |
Ziyue-Zhang <[email protected]> |
rv64v: fix vls issuse queue connection (#2431)
* update fuOpType for vload and vstore
* add vpu connection for vload and vstore issue queue
|
| #
c4501a6f |
| 25-Oct-2023 |
Ziyue-Zhang <[email protected]> |
rv64v: add vlsu decoder (#2425)
* rv64v: support uop split for unit-strided and strided load/store
* rv64v: support uop split for indexed load/store
* rv64v: support fuOp for vls/vst
|
| #
d6059658 |
| 07-Nov-2023 |
Ziyue Zhang <[email protected]> |
rv64v: support all opivi instructions use i2v
|
| #
0a34fc22 |
| 03-Nov-2023 |
Ziyue Zhang <[email protected]> |
rv64v: fix implementation for vmvnr
|
| #
fc85f18f |
| 25-Oct-2023 |
Ziyue Zhang <[email protected]> |
rv64v: replace i2f by i2v for vector instructions
|
| #
c220745d |
| 13-Oct-2023 |
Tang Haojin <[email protected]> |
MemBlock: pass atomic exception through load port (#2381)
|
| #
4b0d80d8 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
Merge upstream/master into tmp-backend-merge-master
|
| #
72d67441 |
| 08-Oct-2023 |
Xuan Hu <[email protected]> |
vector,decode: fix vector insts' src type
* lsrc(2) is assigned to vd if the inst is vector instruction
* set src type of no-used src of vector inst to SrcType.no
|
| #
b94b1889 |
| 13-Sep-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: support vfredosum vfwredosum
|
| #
8891a219 |
| 08-Oct-2023 |
Yinan Xu <[email protected]> |
Bump rocket-chip (#2353)
|
| #
935edac4 |
| 21-Sep-2023 |
Tang Haojin <[email protected]> |
chore: remove deprecated brackets, APIs, etc. (#2321)
|
| #
582849ff |
| 02-Sep-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: support unordered vfreduction
|
| #
54711376 |
| 28-Aug-2023 |
sinsanction <[email protected]> |
Backend, Fusion: support instruction fusion case 'lui + addiw'
|
| #
fe528fd6 |
| 25-Aug-2023 |
sinsanction <[email protected]> |
Backend, Fusion: support instruction fusion case 'lui + addi'
|
| #
b92c5693 |
| 16-Aug-2023 |
Tang Haojin <[email protected]> |
utility: use unified `MemReqSource` (#2243)
|
| #
c61abc0c |
| 06-Aug-2023 |
Xuan Hu <[email protected]> |
merge master into new-backend
Todo: fix error
|
| #
f06d6d60 |
| 14-Jul-2023 |
xiaofeibao-xjtu <[email protected]> |
exu: vfalu support vfcmp vfmerge vfclass
|
| #
3748ec56 |
| 11-Jul-2023 |
xiaofeibao-xjtu <[email protected]> |
exu:vfalu support vfwadd.vv/vf/wv/wf
|