1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 def no = "b000".U // this src read no reg but cannot be Any value 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 51 def apply() = UInt(3.W) 52 } 53 54 object SrcState { 55 def busy = "b0".U 56 def rdy = "b1".U 57 // def specRdy = "b10".U // speculative ready, for future use 58 def apply() = UInt(1.W) 59 60 def isReady(state: UInt): Bool = state === this.rdy 61 def isBusy(state: UInt): Bool = state === this.busy 62 } 63 64 def FuOpTypeWidth = 9 65 object FuOpType { 66 def apply() = UInt(FuOpTypeWidth.W) 67 def X = BitPat("b00000000") 68 } 69 70 object VlduType { 71 def dummy = "b0000".U 72 def vle = "b0001".U 73 def vlse = "b0010".U 74 def vluxe = "b0011".U 75 def vloxe = "b0100".U 76 def vleff = "b0101".U 77 def vlm = "b0110".U 78 def vlr = "b0111".U 79 } 80 81 object VstuType { 82 def dummy = "b0000".U 83 def vse = "b1001".U 84 def vsse = "b1010".U 85 def vsuxe = "b1011".U 86 def vsoxe = "b1100".U 87 def vseff = "b1101".U 88 def vsm = "b1110".U 89 def vsr = "b1111".U 90 } 91 92 object IF2VectorType { 93 // use last 3 bits for vsew 94 def i2vector = "b00_00".U 95 def f2vector = "b00_01".U 96 def imm2vector = "b00_10".U 97 def permImm2vector = "b00_11".U 98 } 99 100 object CommitType { 101 def NORMAL = "b000".U // int/fp 102 def BRANCH = "b001".U // branch 103 def LOAD = "b010".U // load 104 def STORE = "b011".U // store 105 106 def apply() = UInt(3.W) 107 def isFused(commitType: UInt): Bool = commitType(2) 108 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 109 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 110 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 111 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 112 } 113 114 object RedirectLevel { 115 def flushAfter = "b0".U 116 def flush = "b1".U 117 118 def apply() = UInt(1.W) 119 // def isUnconditional(level: UInt) = level(1) 120 def flushItself(level: UInt) = level(0) 121 // def isException(level: UInt) = level(1) && level(0) 122 } 123 124 object ExceptionVec { 125 val ExceptionVecSize = 16 126 def apply() = Vec(ExceptionVecSize, Bool()) 127 } 128 129 object PMAMode { 130 def R = "b1".U << 0 //readable 131 def W = "b1".U << 1 //writeable 132 def X = "b1".U << 2 //executable 133 def I = "b1".U << 3 //cacheable: icache 134 def D = "b1".U << 4 //cacheable: dcache 135 def S = "b1".U << 5 //enable speculative access 136 def A = "b1".U << 6 //enable atomic operation, A imply R & W 137 def C = "b1".U << 7 //if it is cacheable is configable 138 def Reserved = "b0".U 139 140 def apply() = UInt(7.W) 141 142 def read(mode: UInt) = mode(0) 143 def write(mode: UInt) = mode(1) 144 def execute(mode: UInt) = mode(2) 145 def icache(mode: UInt) = mode(3) 146 def dcache(mode: UInt) = mode(4) 147 def speculate(mode: UInt) = mode(5) 148 def atomic(mode: UInt) = mode(6) 149 def configable_cache(mode: UInt) = mode(7) 150 151 def strToMode(s: String) = { 152 var result = 0.U(8.W) 153 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 154 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 155 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 156 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 157 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 158 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 159 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 160 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 161 result 162 } 163 } 164 165 166 object CSROpType { 167 def jmp = "b000".U 168 def wrt = "b001".U 169 def set = "b010".U 170 def clr = "b011".U 171 def wfi = "b100".U 172 def wrti = "b101".U 173 def seti = "b110".U 174 def clri = "b111".U 175 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 176 } 177 178 // jump 179 object JumpOpType { 180 def jal = "b00".U 181 def jalr = "b01".U 182 def auipc = "b10".U 183// def call = "b11_011".U 184// def ret = "b11_100".U 185 def jumpOpisJalr(op: UInt) = op(0) 186 def jumpOpisAuipc(op: UInt) = op(1) 187 } 188 189 object FenceOpType { 190 def fence = "b10000".U 191 def sfence = "b10001".U 192 def fencei = "b10010".U 193 def nofence= "b00000".U 194 } 195 196 object ALUOpType { 197 // shift optype 198 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 199 def sll = "b000_0001".U // sll: src1 << src2 200 201 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 202 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 203 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 204 205 def srl = "b000_0101".U // srl: src1 >> src2 206 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 207 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 208 209 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 210 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 211 212 // RV64 32bit optype 213 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 214 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 215 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 216 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 217 218 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 219 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 220 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 221 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 222 223 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 224 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 225 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 226 def rolw = "b001_1100".U 227 def rorw = "b001_1101".U 228 229 // ADD-op 230 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 231 def add = "b010_0001".U // add: src1 + src2 232 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 233 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 234 235 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 236 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 237 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 238 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 239 240 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 241 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 242 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 243 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 244 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 245 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 246 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 247 248 // SUB-op: src1 - src2 249 def sub = "b011_0000".U 250 def sltu = "b011_0001".U 251 def slt = "b011_0010".U 252 def maxu = "b011_0100".U 253 def minu = "b011_0101".U 254 def max = "b011_0110".U 255 def min = "b011_0111".U 256 257 // branch 258 def beq = "b111_0000".U 259 def bne = "b111_0010".U 260 def blt = "b111_1000".U 261 def bge = "b111_1010".U 262 def bltu = "b111_1100".U 263 def bgeu = "b111_1110".U 264 265 // misc optype 266 def and = "b100_0000".U 267 def andn = "b100_0001".U 268 def or = "b100_0010".U 269 def orn = "b100_0011".U 270 def xor = "b100_0100".U 271 def xnor = "b100_0101".U 272 def orcb = "b100_0110".U 273 274 def sextb = "b100_1000".U 275 def packh = "b100_1001".U 276 def sexth = "b100_1010".U 277 def packw = "b100_1011".U 278 279 def revb = "b101_0000".U 280 def rev8 = "b101_0001".U 281 def pack = "b101_0010".U 282 def orh48 = "b101_0011".U 283 284 def szewl1 = "b101_1000".U 285 def szewl2 = "b101_1001".U 286 def szewl3 = "b101_1010".U 287 def byte2 = "b101_1011".U 288 289 def andlsb = "b110_0000".U 290 def andzexth = "b110_0001".U 291 def orlsb = "b110_0010".U 292 def orzexth = "b110_0011".U 293 def xorlsb = "b110_0100".U 294 def xorzexth = "b110_0101".U 295 def orcblsb = "b110_0110".U 296 def orcbzexth = "b110_0111".U 297 298 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 299 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 300 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 301 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 302 303 def apply() = UInt(FuOpTypeWidth.W) 304 } 305 306 object VSETOpType { 307 val setVlmaxBit = 0 308 val keepVlBit = 1 309 // destTypeBit == 0: write vl to rd 310 // destTypeBit == 1: write vconfig 311 val destTypeBit = 5 312 313 // vsetvli's uop 314 // rs1!=x0, normal 315 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 316 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 317 def uvsetvcfg_xi = "b1010_0000".U 318 def uvsetrd_xi = "b1000_0000".U 319 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 320 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 321 // uop1: w(rd) | vlmax, vtypei -> x[rd] 322 def uvsetvcfg_vlmax_i = "b1010_0001".U 323 def uvsetrd_vlmax_i = "b1000_0001".U 324 // rs1==x0, rd==x0, keep vl, set vtype 325 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 326 def uvsetvcfg_keep_v = "b1010_0010".U 327 328 // vsetvl's uop 329 // rs1!=x0, normal 330 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 331 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 332 def uvsetvcfg_xx = "b0110_0000".U 333 def uvsetrd_xx = "b0100_0000".U 334 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 335 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 336 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 337 def uvsetvcfg_vlmax_x = "b0110_0001".U 338 def uvsetrd_vlmax_x = "b0100_0001".U 339 // rs1==x0, rd==x0, keep vl, set vtype 340 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 341 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 342 def uvmv_v_x = "b0110_0010".U 343 def uvsetvcfg_vv = "b0111_0010".U 344 345 // vsetivli's uop 346 // uop0: w(vconfig) | vli, vtypei -> vconfig 347 // uop1: w(rd) | vli, vtypei -> x[rd] 348 def uvsetvcfg_ii = "b0010_0000".U 349 def uvsetrd_ii = "b0000_0000".U 350 351 def isVsetvl (func: UInt) = func(6) 352 def isVsetvli (func: UInt) = func(7) 353 def isVsetivli(func: UInt) = func(7, 6) === 0.U 354 def isNormal (func: UInt) = func(1, 0) === 0.U 355 def isSetVlmax(func: UInt) = func(setVlmaxBit) 356 def isKeepVl (func: UInt) = func(keepVlBit) 357 // RG: region 358 def writeIntRG(func: UInt) = !func(5) 359 def writeVecRG(func: UInt) = func(5) 360 def readIntRG (func: UInt) = !func(4) 361 def readVecRG (func: UInt) = func(4) 362 // modify fuOpType 363 def switchDest(func: UInt) = func ^ (1 << destTypeBit).U 364 def keepVl(func: UInt) = func | (1 << keepVlBit).U 365 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 366 } 367 368 object BRUOpType { 369 // branch 370 def beq = "b000_000".U 371 def bne = "b000_001".U 372 def blt = "b000_100".U 373 def bge = "b000_101".U 374 def bltu = "b001_000".U 375 def bgeu = "b001_001".U 376 377 def getBranchType(func: UInt) = func(3, 1) 378 def isBranchInvert(func: UInt) = func(0) 379 } 380 381 object MULOpType { 382 // mul 383 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 384 def mul = "b00000".U 385 def mulh = "b00001".U 386 def mulhsu = "b00010".U 387 def mulhu = "b00011".U 388 def mulw = "b00100".U 389 390 def mulw7 = "b01100".U 391 def isSign(op: UInt) = !op(1) 392 def isW(op: UInt) = op(2) 393 def isH(op: UInt) = op(1, 0) =/= 0.U 394 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 395 } 396 397 object DIVOpType { 398 // div 399 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 400 def div = "b10000".U 401 def divu = "b10010".U 402 def rem = "b10001".U 403 def remu = "b10011".U 404 405 def divw = "b10100".U 406 def divuw = "b10110".U 407 def remw = "b10101".U 408 def remuw = "b10111".U 409 410 def isSign(op: UInt) = !op(1) 411 def isW(op: UInt) = op(2) 412 def isH(op: UInt) = op(0) 413 } 414 415 object MDUOpType { 416 // mul 417 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 418 def mul = "b00000".U 419 def mulh = "b00001".U 420 def mulhsu = "b00010".U 421 def mulhu = "b00011".U 422 def mulw = "b00100".U 423 424 def mulw7 = "b01100".U 425 426 // div 427 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 428 def div = "b10000".U 429 def divu = "b10010".U 430 def rem = "b10001".U 431 def remu = "b10011".U 432 433 def divw = "b10100".U 434 def divuw = "b10110".U 435 def remw = "b10101".U 436 def remuw = "b10111".U 437 438 def isMul(op: UInt) = !op(4) 439 def isDiv(op: UInt) = op(4) 440 441 def isDivSign(op: UInt) = isDiv(op) && !op(1) 442 def isW(op: UInt) = op(2) 443 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 444 def getMulOp(op: UInt) = op(1, 0) 445 } 446 447 object LSUOpType { 448 // load pipeline 449 450 // normal load 451 // Note: bit(1, 0) are size, DO NOT CHANGE 452 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 453 def lb = "b0000".U 454 def lh = "b0001".U 455 def lw = "b0010".U 456 def ld = "b0011".U 457 def lbu = "b0100".U 458 def lhu = "b0101".U 459 def lwu = "b0110".U 460 461 // Zicbop software prefetch 462 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 463 def prefetch_i = "b1000".U // TODO 464 def prefetch_r = "b1001".U 465 def prefetch_w = "b1010".U 466 467 def isPrefetch(op: UInt): Bool = op(3) 468 469 // store pipeline 470 // normal store 471 // bit encoding: | store 00 | size(2bit) | 472 def sb = "b0000".U 473 def sh = "b0001".U 474 def sw = "b0010".U 475 def sd = "b0011".U 476 477 // l1 cache op 478 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 479 def cbo_zero = "b0111".U 480 481 // llc op 482 // bit encoding: | prefetch 11 | suboptype(2bit) | 483 def cbo_clean = "b1100".U 484 def cbo_flush = "b1101".U 485 def cbo_inval = "b1110".U 486 487 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 488 489 // atomics 490 // bit(1, 0) are size 491 // since atomics use a different fu type 492 // so we can safely reuse other load/store's encodings 493 // bit encoding: | optype(4bit) | size (2bit) | 494 def lr_w = "b000010".U 495 def sc_w = "b000110".U 496 def amoswap_w = "b001010".U 497 def amoadd_w = "b001110".U 498 def amoxor_w = "b010010".U 499 def amoand_w = "b010110".U 500 def amoor_w = "b011010".U 501 def amomin_w = "b011110".U 502 def amomax_w = "b100010".U 503 def amominu_w = "b100110".U 504 def amomaxu_w = "b101010".U 505 506 def lr_d = "b000011".U 507 def sc_d = "b000111".U 508 def amoswap_d = "b001011".U 509 def amoadd_d = "b001111".U 510 def amoxor_d = "b010011".U 511 def amoand_d = "b010111".U 512 def amoor_d = "b011011".U 513 def amomin_d = "b011111".U 514 def amomax_d = "b100011".U 515 def amominu_d = "b100111".U 516 def amomaxu_d = "b101011".U 517 518 def size(op: UInt) = op(1,0) 519 } 520 521 object BKUOpType { 522 523 def clmul = "b000000".U 524 def clmulh = "b000001".U 525 def clmulr = "b000010".U 526 def xpermn = "b000100".U 527 def xpermb = "b000101".U 528 529 def clz = "b001000".U 530 def clzw = "b001001".U 531 def ctz = "b001010".U 532 def ctzw = "b001011".U 533 def cpop = "b001100".U 534 def cpopw = "b001101".U 535 536 // 01xxxx is reserve 537 def aes64es = "b100000".U 538 def aes64esm = "b100001".U 539 def aes64ds = "b100010".U 540 def aes64dsm = "b100011".U 541 def aes64im = "b100100".U 542 def aes64ks1i = "b100101".U 543 def aes64ks2 = "b100110".U 544 545 // merge to two instruction sm4ks & sm4ed 546 def sm4ed0 = "b101000".U 547 def sm4ed1 = "b101001".U 548 def sm4ed2 = "b101010".U 549 def sm4ed3 = "b101011".U 550 def sm4ks0 = "b101100".U 551 def sm4ks1 = "b101101".U 552 def sm4ks2 = "b101110".U 553 def sm4ks3 = "b101111".U 554 555 def sha256sum0 = "b110000".U 556 def sha256sum1 = "b110001".U 557 def sha256sig0 = "b110010".U 558 def sha256sig1 = "b110011".U 559 def sha512sum0 = "b110100".U 560 def sha512sum1 = "b110101".U 561 def sha512sig0 = "b110110".U 562 def sha512sig1 = "b110111".U 563 564 def sm3p0 = "b111000".U 565 def sm3p1 = "b111001".U 566 } 567 568 object BTBtype { 569 def B = "b00".U // branch 570 def J = "b01".U // jump 571 def I = "b10".U // indirect 572 def R = "b11".U // return 573 574 def apply() = UInt(2.W) 575 } 576 577 object SelImm { 578 def IMM_X = "b0111".U 579 def IMM_S = "b1110".U 580 def IMM_SB = "b0001".U 581 def IMM_U = "b0010".U 582 def IMM_UJ = "b0011".U 583 def IMM_I = "b0100".U 584 def IMM_Z = "b0101".U 585 def INVALID_INSTR = "b0110".U 586 def IMM_B6 = "b1000".U 587 588 def IMM_OPIVIS = "b1001".U 589 def IMM_OPIVIU = "b1010".U 590 def IMM_VSETVLI = "b1100".U 591 def IMM_VSETIVLI = "b1101".U 592 def IMM_LUI32 = "b1011".U 593 594 def X = BitPat("b0000") 595 596 def apply() = UInt(4.W) 597 598 def mkString(immType: UInt) : String = { 599 val strMap = Map( 600 IMM_S.litValue -> "S", 601 IMM_SB.litValue -> "SB", 602 IMM_U.litValue -> "U", 603 IMM_UJ.litValue -> "UJ", 604 IMM_I.litValue -> "I", 605 IMM_Z.litValue -> "Z", 606 IMM_B6.litValue -> "B6", 607 IMM_OPIVIS.litValue -> "VIS", 608 IMM_OPIVIU.litValue -> "VIU", 609 IMM_VSETVLI.litValue -> "VSETVLI", 610 IMM_VSETIVLI.litValue -> "VSETIVLI", 611 IMM_LUI32.litValue -> "LUI32", 612 INVALID_INSTR.litValue -> "INVALID", 613 ) 614 strMap(immType.litValue) 615 } 616 } 617 618 object UopSplitType { 619 def SCA_SIM = "b000000".U // 620 def DIR = "b010001".U // dirty: vset 621 def VEC_VVV = "b010010".U // VEC_VVV 622 def VEC_VXV = "b010011".U // VEC_VXV 623 def VEC_0XV = "b010100".U // VEC_0XV 624 def VEC_VVW = "b010101".U // VEC_VVW 625 def VEC_WVW = "b010110".U // VEC_WVW 626 def VEC_VXW = "b010111".U // VEC_VXW 627 def VEC_WXW = "b011000".U // VEC_WXW 628 def VEC_WVV = "b011001".U // VEC_WVV 629 def VEC_WXV = "b011010".U // VEC_WXV 630 def VEC_EXT2 = "b011011".U // VF2 0 -> V 631 def VEC_EXT4 = "b011100".U // VF4 0 -> V 632 def VEC_EXT8 = "b011101".U // VF8 0 -> V 633 def VEC_VVM = "b011110".U // VEC_VVM 634 def VEC_VXM = "b011111".U // VEC_VXM 635 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 636 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 637 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 638 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 639 def VEC_VRED = "b100100".U // VEC_VRED 640 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 641 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 642 def VEC_M0X = "b101001".U // VEC_M0X 0MV 643 def VEC_MVV = "b101010".U // VEC_MVV VMV 644 def VEC_M0X_VFIRST = "b101011".U // 645 def VEC_VWW = "b101100".U // 646 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 647 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 648 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 649 def VEC_COMPRESS = "b110000".U // vcompress.vm 650 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 651 def VEC_S_LDST = "b110010".U // vector strided load/store 652 def VEC_I_LDST = "b110011".U // vector indexed load/store 653 def VEC_VFV = "b111000".U // VEC_VFV 654 def VEC_VFW = "b111001".U // VEC_VFW 655 def VEC_WFW = "b111010".U // VEC_WVW 656 def VEC_VFM = "b111011".U // VEC_VFM 657 def VEC_VFRED = "b111100".U // VEC_VFRED 658 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 659 def VEC_M0M = "b000000".U // VEC_M0M 660 def VEC_MMM = "b000000".U // VEC_MMM 661 def VEC_MVNR = "b000100".U // vmvnr 662 def dummy = "b111111".U 663 664 def X = BitPat("b000000") 665 666 def apply() = UInt(6.W) 667 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 668 } 669 670 object ExceptionNO { 671 def instrAddrMisaligned = 0 672 def instrAccessFault = 1 673 def illegalInstr = 2 674 def breakPoint = 3 675 def loadAddrMisaligned = 4 676 def loadAccessFault = 5 677 def storeAddrMisaligned = 6 678 def storeAccessFault = 7 679 def ecallU = 8 680 def ecallS = 9 681 def ecallM = 11 682 def instrPageFault = 12 683 def loadPageFault = 13 684 // def singleStep = 14 685 def storePageFault = 15 686 def priorities = Seq( 687 breakPoint, // TODO: different BP has different priority 688 instrPageFault, 689 instrAccessFault, 690 illegalInstr, 691 instrAddrMisaligned, 692 ecallM, ecallS, ecallU, 693 storeAddrMisaligned, 694 loadAddrMisaligned, 695 storePageFault, 696 loadPageFault, 697 storeAccessFault, 698 loadAccessFault 699 ) 700 def all = priorities.distinct.sorted 701 def frontendSet = Seq( 702 instrAddrMisaligned, 703 instrAccessFault, 704 illegalInstr, 705 instrPageFault 706 ) 707 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 708 val new_vec = Wire(ExceptionVec()) 709 new_vec.foreach(_ := false.B) 710 select.foreach(i => new_vec(i) := vec(i)) 711 new_vec 712 } 713 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 714 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 715 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 716 partialSelect(vec, fuConfig.exceptionOut) 717 } 718 719 object TopDownCounters extends Enumeration { 720 val NoStall = Value("NoStall") // Base 721 // frontend 722 val OverrideBubble = Value("OverrideBubble") 723 val FtqUpdateBubble = Value("FtqUpdateBubble") 724 // val ControlRedirectBubble = Value("ControlRedirectBubble") 725 val TAGEMissBubble = Value("TAGEMissBubble") 726 val SCMissBubble = Value("SCMissBubble") 727 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 728 val RASMissBubble = Value("RASMissBubble") 729 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 730 val OtherRedirectBubble = Value("OtherRedirectBubble") 731 val FtqFullStall = Value("FtqFullStall") 732 733 val ICacheMissBubble = Value("ICacheMissBubble") 734 val ITLBMissBubble = Value("ITLBMissBubble") 735 val BTBMissBubble = Value("BTBMissBubble") 736 val FetchFragBubble = Value("FetchFragBubble") 737 738 // backend 739 // long inst stall at rob head 740 val DivStall = Value("DivStall") // int div, float div/sqrt 741 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 742 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 743 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 744 // freelist full 745 val IntFlStall = Value("IntFlStall") 746 val FpFlStall = Value("FpFlStall") 747 // dispatch queue full 748 val IntDqStall = Value("IntDqStall") 749 val FpDqStall = Value("FpDqStall") 750 val LsDqStall = Value("LsDqStall") 751 752 // memblock 753 val LoadTLBStall = Value("LoadTLBStall") 754 val LoadL1Stall = Value("LoadL1Stall") 755 val LoadL2Stall = Value("LoadL2Stall") 756 val LoadL3Stall = Value("LoadL3Stall") 757 val LoadMemStall = Value("LoadMemStall") 758 val StoreStall = Value("StoreStall") // include store tlb miss 759 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 760 761 // xs replay (different to gem5) 762 val LoadVioReplayStall = Value("LoadVioReplayStall") 763 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 764 765 // bad speculation 766 val ControlRecoveryStall = Value("ControlRecoveryStall") 767 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 768 val OtherRecoveryStall = Value("OtherRecoveryStall") 769 770 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 771 772 val OtherCoreStall = Value("OtherCoreStall") 773 774 val NumStallReasons = Value("NumStallReasons") 775 } 776} 777