1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import xiangshan.ExceptionNO._ 20import xiangshan.backend.fu._ 21import xiangshan.backend.fu.fpu._ 22import xiangshan.backend.fu.vector._ 23import xiangshan.backend.issue._ 24import xiangshan.backend.fu.FuConfig 25 26package object xiangshan { 27 object SrcType { 28 def imm = "b000".U 29 def pc = "b000".U 30 def xp = "b001".U 31 def fp = "b010".U 32 def vp = "b100".U 33 34 // alias 35 def reg = this.xp 36 def DC = imm // Don't Care 37 def X = BitPat("b000") 38 39 def isPc(srcType: UInt) = srcType===pc 40 def isImm(srcType: UInt) = srcType===imm 41 def isReg(srcType: UInt) = srcType(0) 42 def isXp(srcType: UInt) = srcType(0) 43 def isFp(srcType: UInt) = srcType(1) 44 def isVp(srcType: UInt) = srcType(2) 45 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 46 def isNotReg(srcType: UInt): Bool = !srcType.orR 47 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 48 def apply() = UInt(3.W) 49 } 50 51 object SrcState { 52 def busy = "b0".U 53 def rdy = "b1".U 54 // def specRdy = "b10".U // speculative ready, for future use 55 def apply() = UInt(1.W) 56 57 def isReady(state: UInt): Bool = state === this.rdy 58 def isBusy(state: UInt): Bool = state === this.busy 59 } 60 61 def FuOpTypeWidth = 9 62 object FuOpType { 63 def apply() = UInt(FuOpTypeWidth.W) 64 def X = BitPat("b00000000") 65 } 66 67 object VlduType { 68 def dummy = 0.U 69 } 70 71 object VstuType { 72 def dummy = 0.U 73 } 74 75 object CommitType { 76 def NORMAL = "b000".U // int/fp 77 def BRANCH = "b001".U // branch 78 def LOAD = "b010".U // load 79 def STORE = "b011".U // store 80 81 def apply() = UInt(3.W) 82 def isFused(commitType: UInt): Bool = commitType(2) 83 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 84 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 85 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 86 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 87 } 88 89 object RedirectLevel { 90 def flushAfter = "b0".U 91 def flush = "b1".U 92 93 def apply() = UInt(1.W) 94 // def isUnconditional(level: UInt) = level(1) 95 def flushItself(level: UInt) = level(0) 96 // def isException(level: UInt) = level(1) && level(0) 97 } 98 99 object ExceptionVec { 100 val ExceptionVecSize = 16 101 def apply() = Vec(ExceptionVecSize, Bool()) 102 } 103 104 object PMAMode { 105 def R = "b1".U << 0 //readable 106 def W = "b1".U << 1 //writeable 107 def X = "b1".U << 2 //executable 108 def I = "b1".U << 3 //cacheable: icache 109 def D = "b1".U << 4 //cacheable: dcache 110 def S = "b1".U << 5 //enable speculative access 111 def A = "b1".U << 6 //enable atomic operation, A imply R & W 112 def C = "b1".U << 7 //if it is cacheable is configable 113 def Reserved = "b0".U 114 115 def apply() = UInt(7.W) 116 117 def read(mode: UInt) = mode(0) 118 def write(mode: UInt) = mode(1) 119 def execute(mode: UInt) = mode(2) 120 def icache(mode: UInt) = mode(3) 121 def dcache(mode: UInt) = mode(4) 122 def speculate(mode: UInt) = mode(5) 123 def atomic(mode: UInt) = mode(6) 124 def configable_cache(mode: UInt) = mode(7) 125 126 def strToMode(s: String) = { 127 var result = 0.U(8.W) 128 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 129 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 130 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 131 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 132 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 133 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 134 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 135 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 136 result 137 } 138 } 139 140 141 object CSROpType { 142 def jmp = "b000".U 143 def wrt = "b001".U 144 def set = "b010".U 145 def clr = "b011".U 146 def wfi = "b100".U 147 def wrti = "b101".U 148 def seti = "b110".U 149 def clri = "b111".U 150 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 151 } 152 153 // jump 154 object JumpOpType { 155 def jal = "b00".U 156 def jalr = "b01".U 157 def auipc = "b10".U 158// def call = "b11_011".U 159// def ret = "b11_100".U 160 def jumpOpisJalr(op: UInt) = op(0) 161 def jumpOpisAuipc(op: UInt) = op(1) 162 } 163 164 object FenceOpType { 165 def fence = "b10000".U 166 def sfence = "b10001".U 167 def fencei = "b10010".U 168 def nofence= "b00000".U 169 } 170 171 object ALUOpType { 172 // shift optype 173 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 174 def sll = "b000_0001".U // sll: src1 << src2 175 176 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 177 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 178 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 179 180 def srl = "b000_0101".U // srl: src1 >> src2 181 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 182 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 183 184 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 185 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 186 187 // RV64 32bit optype 188 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 189 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 190 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 191 192 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 193 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 194 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 195 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 196 197 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 198 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 199 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 200 def rolw = "b001_1100".U 201 def rorw = "b001_1101".U 202 203 // ADD-op 204 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 205 def add = "b010_0001".U // add: src1 + src2 206 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 207 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 208 209 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 210 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 211 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 212 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 213 214 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 215 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 216 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 217 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 218 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 219 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 220 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 221 222 // SUB-op: src1 - src2 223 def sub = "b011_0000".U 224 def sltu = "b011_0001".U 225 def slt = "b011_0010".U 226 def maxu = "b011_0100".U 227 def minu = "b011_0101".U 228 def max = "b011_0110".U 229 def min = "b011_0111".U 230 231 // branch 232 def beq = "b111_0000".U 233 def bne = "b111_0010".U 234 def blt = "b111_1000".U 235 def bge = "b111_1010".U 236 def bltu = "b111_1100".U 237 def bgeu = "b111_1110".U 238 239 // misc optype 240 def and = "b100_0000".U 241 def andn = "b100_0001".U 242 def or = "b100_0010".U 243 def orn = "b100_0011".U 244 def xor = "b100_0100".U 245 def xnor = "b100_0101".U 246 def orcb = "b100_0110".U 247 248 def sextb = "b100_1000".U 249 def packh = "b100_1001".U 250 def sexth = "b100_1010".U 251 def packw = "b100_1011".U 252 253 def revb = "b101_0000".U 254 def rev8 = "b101_0001".U 255 def pack = "b101_0010".U 256 def orh48 = "b101_0011".U 257 258 def szewl1 = "b101_1000".U 259 def szewl2 = "b101_1001".U 260 def szewl3 = "b101_1010".U 261 def byte2 = "b101_1011".U 262 263 def andlsb = "b110_0000".U 264 def andzexth = "b110_0001".U 265 def orlsb = "b110_0010".U 266 def orzexth = "b110_0011".U 267 def xorlsb = "b110_0100".U 268 def xorzexth = "b110_0101".U 269 def orcblsb = "b110_0110".U 270 def orcbzexth = "b110_0111".U 271 272 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 273 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 274 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 275 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 276 277 def apply() = UInt(FuOpTypeWidth.W) 278 } 279 280 object VSETOpType { 281 val setVlmaxBit = 0 282 val keepVlBit = 1 283 // destTypeBit == 0: write vl to rd 284 // destTypeBit == 1: write vconfig 285 val destTypeBit = 5 286 287 // vsetvli's uop 288 // rs1!=x0, normal 289 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 290 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 291 def uvsetvcfg_xi = "b1010_0000".U 292 def uvsetrd_xi = "b1000_0000".U 293 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 294 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 295 // uop1: w(rd) | vlmax, vtypei -> x[rd] 296 def uvsetvcfg_vlmax_i = "b1010_0001".U 297 def uvsetrd_vlmax_i = "b1000_0001".U 298 // rs1==x0, rd==x0, keep vl, set vtype 299 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 300 def uvsetvcfg_keep_v = "b1010_0010".U 301 302 // vsetvl's uop 303 // rs1!=x0, normal 304 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 305 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 306 def uvsetvcfg_xx = "b0110_0000".U 307 def uvsetrd_xx = "b0100_0000".U 308 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 309 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 310 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 311 def uvsetvcfg_vlmax_x = "b0110_0001".U 312 def uvsetrd_vlmax_x = "b0100_0001".U 313 // rs1==x0, rd==x0, keep vl, set vtype 314 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 315 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 316 def uvmv_v_x = "b0110_0010".U 317 def uvsetvcfg_vv = "b0111_0010".U 318 319 // vsetivli's uop 320 // uop0: w(vconfig) | vli, vtypei -> vconfig 321 // uop1: w(rd) | vli, vtypei -> x[rd] 322 def uvsetvcfg_ii = "b0010_0000".U 323 def uvsetrd_ii = "b0000_0000".U 324 325 def isVsetvl (func: UInt) = func(6) 326 def isVsetvli (func: UInt) = func(7) 327 def isVsetivli(func: UInt) = func(7, 6) === 0.U 328 def isNormal (func: UInt) = func(1, 0) === 0.U 329 def isSetVlmax(func: UInt) = func(setVlmaxBit) 330 def isKeepVl (func: UInt) = func(keepVlBit) 331 // RG: region 332 def writeIntRG(func: UInt) = !func(5) 333 def writeVecRG(func: UInt) = func(5) 334 def readIntRG (func: UInt) = !func(4) 335 def readVecRG (func: UInt) = func(4) 336 // modify fuOpType 337 def switchDest(func: UInt) = func ^ (1 << destTypeBit).U 338 def keepVl(func: UInt) = func | (1 << keepVlBit).U 339 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 340 } 341 342 object BRUOpType { 343 // branch 344 def beq = "b000_000".U 345 def bne = "b000_001".U 346 def blt = "b000_100".U 347 def bge = "b000_101".U 348 def bltu = "b001_000".U 349 def bgeu = "b001_001".U 350 351 def getBranchType(func: UInt) = func(3, 1) 352 def isBranchInvert(func: UInt) = func(0) 353 } 354 355 object MULOpType { 356 // mul 357 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 358 def mul = "b00000".U 359 def mulh = "b00001".U 360 def mulhsu = "b00010".U 361 def mulhu = "b00011".U 362 def mulw = "b00100".U 363 364 def mulw7 = "b01100".U 365 def isSign(op: UInt) = !op(1) 366 def isW(op: UInt) = op(2) 367 def isH(op: UInt) = op(1, 0) =/= 0.U 368 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 369 } 370 371 object DIVOpType { 372 // div 373 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 374 def div = "b10000".U 375 def divu = "b10010".U 376 def rem = "b10001".U 377 def remu = "b10011".U 378 379 def divw = "b10100".U 380 def divuw = "b10110".U 381 def remw = "b10101".U 382 def remuw = "b10111".U 383 384 def isSign(op: UInt) = !op(1) 385 def isW(op: UInt) = op(2) 386 def isH(op: UInt) = op(0) 387 } 388 389 object MDUOpType { 390 // mul 391 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 392 def mul = "b00000".U 393 def mulh = "b00001".U 394 def mulhsu = "b00010".U 395 def mulhu = "b00011".U 396 def mulw = "b00100".U 397 398 def mulw7 = "b01100".U 399 400 // div 401 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 402 def div = "b10000".U 403 def divu = "b10010".U 404 def rem = "b10001".U 405 def remu = "b10011".U 406 407 def divw = "b10100".U 408 def divuw = "b10110".U 409 def remw = "b10101".U 410 def remuw = "b10111".U 411 412 def isMul(op: UInt) = !op(4) 413 def isDiv(op: UInt) = op(4) 414 415 def isDivSign(op: UInt) = isDiv(op) && !op(1) 416 def isW(op: UInt) = op(2) 417 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 418 def getMulOp(op: UInt) = op(1, 0) 419 } 420 421 object LSUOpType { 422 // load pipeline 423 424 // normal load 425 // Note: bit(1, 0) are size, DO NOT CHANGE 426 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 427 def lb = "b0000".U 428 def lh = "b0001".U 429 def lw = "b0010".U 430 def ld = "b0011".U 431 def lbu = "b0100".U 432 def lhu = "b0101".U 433 def lwu = "b0110".U 434 435 // Zicbop software prefetch 436 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 437 def prefetch_i = "b1000".U // TODO 438 def prefetch_r = "b1001".U 439 def prefetch_w = "b1010".U 440 441 def isPrefetch(op: UInt): Bool = op(3) 442 443 // store pipeline 444 // normal store 445 // bit encoding: | store 00 | size(2bit) | 446 def sb = "b0000".U 447 def sh = "b0001".U 448 def sw = "b0010".U 449 def sd = "b0011".U 450 451 // l1 cache op 452 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 453 def cbo_zero = "b0111".U 454 455 // llc op 456 // bit encoding: | prefetch 11 | suboptype(2bit) | 457 def cbo_clean = "b1100".U 458 def cbo_flush = "b1101".U 459 def cbo_inval = "b1110".U 460 461 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 462 463 // atomics 464 // bit(1, 0) are size 465 // since atomics use a different fu type 466 // so we can safely reuse other load/store's encodings 467 // bit encoding: | optype(4bit) | size (2bit) | 468 def lr_w = "b000010".U 469 def sc_w = "b000110".U 470 def amoswap_w = "b001010".U 471 def amoadd_w = "b001110".U 472 def amoxor_w = "b010010".U 473 def amoand_w = "b010110".U 474 def amoor_w = "b011010".U 475 def amomin_w = "b011110".U 476 def amomax_w = "b100010".U 477 def amominu_w = "b100110".U 478 def amomaxu_w = "b101010".U 479 480 def lr_d = "b000011".U 481 def sc_d = "b000111".U 482 def amoswap_d = "b001011".U 483 def amoadd_d = "b001111".U 484 def amoxor_d = "b010011".U 485 def amoand_d = "b010111".U 486 def amoor_d = "b011011".U 487 def amomin_d = "b011111".U 488 def amomax_d = "b100011".U 489 def amominu_d = "b100111".U 490 def amomaxu_d = "b101011".U 491 492 def size(op: UInt) = op(1,0) 493 } 494 495 object BKUOpType { 496 497 def clmul = "b000000".U 498 def clmulh = "b000001".U 499 def clmulr = "b000010".U 500 def xpermn = "b000100".U 501 def xpermb = "b000101".U 502 503 def clz = "b001000".U 504 def clzw = "b001001".U 505 def ctz = "b001010".U 506 def ctzw = "b001011".U 507 def cpop = "b001100".U 508 def cpopw = "b001101".U 509 510 // 01xxxx is reserve 511 def aes64es = "b100000".U 512 def aes64esm = "b100001".U 513 def aes64ds = "b100010".U 514 def aes64dsm = "b100011".U 515 def aes64im = "b100100".U 516 def aes64ks1i = "b100101".U 517 def aes64ks2 = "b100110".U 518 519 // merge to two instruction sm4ks & sm4ed 520 def sm4ed0 = "b101000".U 521 def sm4ed1 = "b101001".U 522 def sm4ed2 = "b101010".U 523 def sm4ed3 = "b101011".U 524 def sm4ks0 = "b101100".U 525 def sm4ks1 = "b101101".U 526 def sm4ks2 = "b101110".U 527 def sm4ks3 = "b101111".U 528 529 def sha256sum0 = "b110000".U 530 def sha256sum1 = "b110001".U 531 def sha256sig0 = "b110010".U 532 def sha256sig1 = "b110011".U 533 def sha512sum0 = "b110100".U 534 def sha512sum1 = "b110101".U 535 def sha512sig0 = "b110110".U 536 def sha512sig1 = "b110111".U 537 538 def sm3p0 = "b111000".U 539 def sm3p1 = "b111001".U 540 } 541 542 object BTBtype { 543 def B = "b00".U // branch 544 def J = "b01".U // jump 545 def I = "b10".U // indirect 546 def R = "b11".U // return 547 548 def apply() = UInt(2.W) 549 } 550 551 object SelImm { 552 def IMM_X = "b0111".U 553 def IMM_S = "b1110".U 554 def IMM_SB = "b0001".U 555 def IMM_U = "b0010".U 556 def IMM_UJ = "b0011".U 557 def IMM_I = "b0100".U 558 def IMM_Z = "b0101".U 559 def INVALID_INSTR = "b0110".U 560 def IMM_B6 = "b1000".U 561 562 def IMM_OPIVIS = "b1001".U 563 def IMM_OPIVIU = "b1010".U 564 def IMM_VSETVLI = "b1100".U 565 def IMM_VSETIVLI = "b1101".U 566 def IMM_LUI32 = "b1011".U 567 568 def X = BitPat("b0000") 569 570 def apply() = UInt(4.W) 571 572 def mkString(immType: UInt) : String = { 573 val strMap = Map( 574 IMM_S.litValue -> "S", 575 IMM_SB.litValue -> "SB", 576 IMM_U.litValue -> "U", 577 IMM_UJ.litValue -> "UJ", 578 IMM_I.litValue -> "I", 579 IMM_Z.litValue -> "Z", 580 IMM_B6.litValue -> "B6", 581 IMM_OPIVIS.litValue -> "VIS", 582 IMM_OPIVIU.litValue -> "VIU", 583 IMM_VSETVLI.litValue -> "VSETVLI", 584 IMM_VSETIVLI.litValue -> "VSETIVLI", 585 IMM_LUI32.litValue -> "LUI32", 586 INVALID_INSTR.litValue -> "INVALID", 587 ) 588 strMap(immType.litValue) 589 } 590 } 591 592 object UopSplitType { 593 def SCA_SIM = "b000000".U // 594 def DIR = "b010001".U // dirty: vset 595 def VEC_VVV = "b010010".U // VEC_VVV 596 def VEC_VXV = "b010011".U // VEC_VXV 597 def VEC_0XV = "b010100".U // VEC_0XV 598 def VEC_VVW = "b010101".U // VEC_VVW 599 def VEC_WVW = "b010110".U // VEC_WVW 600 def VEC_VXW = "b010111".U // VEC_VXW 601 def VEC_WXW = "b011000".U // VEC_WXW 602 def VEC_WVV = "b011001".U // VEC_WVV 603 def VEC_WXV = "b011010".U // VEC_WXV 604 def VEC_EXT2 = "b011011".U // VF2 0 -> V 605 def VEC_EXT4 = "b011100".U // VF4 0 -> V 606 def VEC_EXT8 = "b011101".U // VF8 0 -> V 607 def VEC_VVM = "b011110".U // VEC_VVM 608 def VEC_VXM = "b011111".U // VEC_VXM 609 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 610 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 611 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 612 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 613 def VEC_VRED = "b100100".U // VEC_VRED 614 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 615 def VEC_ISLIDEUP = "b100110".U // VEC_ISLIDEUP 616 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 617 def VEC_ISLIDEDOWN = "b101000".U // VEC_ISLIDEDOWN 618 def VEC_M0X = "b101001".U // VEC_M0X 0MV 619 def VEC_MVV = "b101010".U // VEC_MVV VMV 620 def VEC_M0X_VFIRST = "b101011".U // 621 def VEC_VWW = "b101100".U // 622 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 623 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 624 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 625 def VEC_COMPRESS = "b110000".U // vcompress.vm 626 def VEC_US_LD = "b110001".U // vector unit strided load 627 def VEC_VFV = "b111000".U // VEC_VFV 628 def VEC_VFW = "b111001".U // VEC_VFW 629 def VEC_WFW = "b111010".U // VEC_WVW 630 def VEC_VFM = "b111011".U // VEC_VFM 631 def VEC_M0M = "b000000".U // VEC_M0M 632 def VEC_MMM = "b000000".U // VEC_MMM 633 def dummy = "b111111".U 634 635 def X = BitPat("b000000") 636 637 def apply() = UInt(6.W) 638 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 639 } 640 641 object ExceptionNO { 642 def instrAddrMisaligned = 0 643 def instrAccessFault = 1 644 def illegalInstr = 2 645 def breakPoint = 3 646 def loadAddrMisaligned = 4 647 def loadAccessFault = 5 648 def storeAddrMisaligned = 6 649 def storeAccessFault = 7 650 def ecallU = 8 651 def ecallS = 9 652 def ecallM = 11 653 def instrPageFault = 12 654 def loadPageFault = 13 655 // def singleStep = 14 656 def storePageFault = 15 657 def priorities = Seq( 658 breakPoint, // TODO: different BP has different priority 659 instrPageFault, 660 instrAccessFault, 661 illegalInstr, 662 instrAddrMisaligned, 663 ecallM, ecallS, ecallU, 664 storeAddrMisaligned, 665 loadAddrMisaligned, 666 storePageFault, 667 loadPageFault, 668 storeAccessFault, 669 loadAccessFault 670 ) 671 def all = priorities.distinct.sorted 672 def frontendSet = Seq( 673 instrAddrMisaligned, 674 instrAccessFault, 675 illegalInstr, 676 instrPageFault 677 ) 678 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 679 val new_vec = Wire(ExceptionVec()) 680 new_vec.foreach(_ := false.B) 681 select.foreach(i => new_vec(i) := vec(i)) 682 new_vec 683 } 684 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 685 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 686 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 687 partialSelect(vec, fuConfig.exceptionOut) 688 } 689 690 // indicates where the memory access request comes from 691 // a dupliacte of this is in HuanCun.common and CoupledL2.common 692 // TODO: consider moving it to Utility, so that they could share the same definition 693 object MemReqSource extends Enumeration { 694 val NoWhere = Value("NoWhere") 695 696 val CPUInst = Value("CPUInst") 697 val CPULoadData = Value("CPULoadData") 698 val CPUStoreData = Value("CPUStoreData") 699 val CPUAtomicData = Value("CPUAtomicData") 700 val L1InstPrefetch = Value("L1InstPrefetch") 701 val L1DataPrefetch = Value("L1DataPrefetch") 702 val PTW = Value("PTW") 703 val L2Prefetch = Value("L2Prefetch") 704 val ReqSourceCount = Value("ReqSourceCount") 705 706 val reqSourceBits = log2Ceil(ReqSourceCount.id) 707 } 708 709 object TopDownCounters extends Enumeration { 710 val NoStall = Value("NoStall") // Base 711 // frontend 712 val OverrideBubble = Value("OverrideBubble") 713 val FtqUpdateBubble = Value("FtqUpdateBubble") 714 // val ControlRedirectBubble = Value("ControlRedirectBubble") 715 val TAGEMissBubble = Value("TAGEMissBubble") 716 val SCMissBubble = Value("SCMissBubble") 717 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 718 val RASMissBubble = Value("RASMissBubble") 719 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 720 val OtherRedirectBubble = Value("OtherRedirectBubble") 721 val FtqFullStall = Value("FtqFullStall") 722 723 val ICacheMissBubble = Value("ICacheMissBubble") 724 val ITLBMissBubble = Value("ITLBMissBubble") 725 val BTBMissBubble = Value("BTBMissBubble") 726 val FetchFragBubble = Value("FetchFragBubble") 727 728 // backend 729 // long inst stall at rob head 730 val DivStall = Value("DivStall") // int div, float div/sqrt 731 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 732 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 733 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 734 // freelist full 735 val IntFlStall = Value("IntFlStall") 736 val FpFlStall = Value("FpFlStall") 737 // dispatch queue full 738 val IntDqStall = Value("IntDqStall") 739 val FpDqStall = Value("FpDqStall") 740 val LsDqStall = Value("LsDqStall") 741 742 // memblock 743 val LoadTLBStall = Value("LoadTLBStall") 744 val LoadL1Stall = Value("LoadL1Stall") 745 val LoadL2Stall = Value("LoadL2Stall") 746 val LoadL3Stall = Value("LoadL3Stall") 747 val LoadMemStall = Value("LoadMemStall") 748 val StoreStall = Value("StoreStall") // include store tlb miss 749 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 750 751 // xs replay (different to gem5) 752 val LoadVioReplayStall = Value("LoadVioReplayStall") 753 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 754 755 // bad speculation 756 val ControlRecoveryStall = Value("ControlRecoveryStall") 757 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 758 val OtherRecoveryStall = Value("OtherRecoveryStall") 759 760 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 761 762 val OtherCoreStall = Value("OtherCoreStall") 763 764 val NumStallReasons = Value("NumStallReasons") 765 } 766} 767