1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import xiangshan.ExceptionNO._ 20import xiangshan.backend.fu._ 21import xiangshan.backend.fu.fpu._ 22import xiangshan.backend.fu.vector._ 23import xiangshan.backend.issue._ 24import xiangshan.backend.fu.FuConfig 25 26package object xiangshan { 27 object SrcType { 28 def imm = "b000".U 29 def pc = "b000".U 30 def xp = "b001".U 31 def fp = "b010".U 32 def vp = "b100".U 33 def no = "b000".U // this src read no reg but cannot be Any value 34 35 // alias 36 def reg = this.xp 37 def DC = imm // Don't Care 38 def X = BitPat("b000") 39 40 def isPc(srcType: UInt) = srcType===pc 41 def isImm(srcType: UInt) = srcType===imm 42 def isReg(srcType: UInt) = srcType(0) 43 def isXp(srcType: UInt) = srcType(0) 44 def isFp(srcType: UInt) = srcType(1) 45 def isVp(srcType: UInt) = srcType(2) 46 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 47 def isNotReg(srcType: UInt): Bool = !srcType.orR 48 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 49 def apply() = UInt(3.W) 50 } 51 52 object SrcState { 53 def busy = "b0".U 54 def rdy = "b1".U 55 // def specRdy = "b10".U // speculative ready, for future use 56 def apply() = UInt(1.W) 57 58 def isReady(state: UInt): Bool = state === this.rdy 59 def isBusy(state: UInt): Bool = state === this.busy 60 } 61 62 def FuOpTypeWidth = 9 63 object FuOpType { 64 def apply() = UInt(FuOpTypeWidth.W) 65 def X = BitPat("b00000000") 66 } 67 68 object VlduType { 69 def dummy = 0.U 70 } 71 72 object VstuType { 73 def dummy = 0.U 74 } 75 76 object CommitType { 77 def NORMAL = "b000".U // int/fp 78 def BRANCH = "b001".U // branch 79 def LOAD = "b010".U // load 80 def STORE = "b011".U // store 81 82 def apply() = UInt(3.W) 83 def isFused(commitType: UInt): Bool = commitType(2) 84 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 85 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 86 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 87 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 88 } 89 90 object RedirectLevel { 91 def flushAfter = "b0".U 92 def flush = "b1".U 93 94 def apply() = UInt(1.W) 95 // def isUnconditional(level: UInt) = level(1) 96 def flushItself(level: UInt) = level(0) 97 // def isException(level: UInt) = level(1) && level(0) 98 } 99 100 object ExceptionVec { 101 val ExceptionVecSize = 16 102 def apply() = Vec(ExceptionVecSize, Bool()) 103 } 104 105 object PMAMode { 106 def R = "b1".U << 0 //readable 107 def W = "b1".U << 1 //writeable 108 def X = "b1".U << 2 //executable 109 def I = "b1".U << 3 //cacheable: icache 110 def D = "b1".U << 4 //cacheable: dcache 111 def S = "b1".U << 5 //enable speculative access 112 def A = "b1".U << 6 //enable atomic operation, A imply R & W 113 def C = "b1".U << 7 //if it is cacheable is configable 114 def Reserved = "b0".U 115 116 def apply() = UInt(7.W) 117 118 def read(mode: UInt) = mode(0) 119 def write(mode: UInt) = mode(1) 120 def execute(mode: UInt) = mode(2) 121 def icache(mode: UInt) = mode(3) 122 def dcache(mode: UInt) = mode(4) 123 def speculate(mode: UInt) = mode(5) 124 def atomic(mode: UInt) = mode(6) 125 def configable_cache(mode: UInt) = mode(7) 126 127 def strToMode(s: String) = { 128 var result = 0.U(8.W) 129 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 130 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 131 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 132 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 133 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 134 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 135 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 136 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 137 result 138 } 139 } 140 141 142 object CSROpType { 143 def jmp = "b000".U 144 def wrt = "b001".U 145 def set = "b010".U 146 def clr = "b011".U 147 def wfi = "b100".U 148 def wrti = "b101".U 149 def seti = "b110".U 150 def clri = "b111".U 151 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 152 } 153 154 // jump 155 object JumpOpType { 156 def jal = "b00".U 157 def jalr = "b01".U 158 def auipc = "b10".U 159// def call = "b11_011".U 160// def ret = "b11_100".U 161 def jumpOpisJalr(op: UInt) = op(0) 162 def jumpOpisAuipc(op: UInt) = op(1) 163 } 164 165 object FenceOpType { 166 def fence = "b10000".U 167 def sfence = "b10001".U 168 def fencei = "b10010".U 169 def nofence= "b00000".U 170 } 171 172 object ALUOpType { 173 // shift optype 174 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 175 def sll = "b000_0001".U // sll: src1 << src2 176 177 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 178 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 179 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 180 181 def srl = "b000_0101".U // srl: src1 >> src2 182 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 183 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 184 185 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 186 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 187 188 // RV64 32bit optype 189 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 190 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 191 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 192 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 193 194 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 195 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 196 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 197 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 198 199 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 200 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 201 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 202 def rolw = "b001_1100".U 203 def rorw = "b001_1101".U 204 205 // ADD-op 206 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 207 def add = "b010_0001".U // add: src1 + src2 208 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 209 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 210 211 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 212 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 213 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 214 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 215 216 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 217 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 218 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 219 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 220 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 221 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 222 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 223 224 // SUB-op: src1 - src2 225 def sub = "b011_0000".U 226 def sltu = "b011_0001".U 227 def slt = "b011_0010".U 228 def maxu = "b011_0100".U 229 def minu = "b011_0101".U 230 def max = "b011_0110".U 231 def min = "b011_0111".U 232 233 // branch 234 def beq = "b111_0000".U 235 def bne = "b111_0010".U 236 def blt = "b111_1000".U 237 def bge = "b111_1010".U 238 def bltu = "b111_1100".U 239 def bgeu = "b111_1110".U 240 241 // misc optype 242 def and = "b100_0000".U 243 def andn = "b100_0001".U 244 def or = "b100_0010".U 245 def orn = "b100_0011".U 246 def xor = "b100_0100".U 247 def xnor = "b100_0101".U 248 def orcb = "b100_0110".U 249 250 def sextb = "b100_1000".U 251 def packh = "b100_1001".U 252 def sexth = "b100_1010".U 253 def packw = "b100_1011".U 254 255 def revb = "b101_0000".U 256 def rev8 = "b101_0001".U 257 def pack = "b101_0010".U 258 def orh48 = "b101_0011".U 259 260 def szewl1 = "b101_1000".U 261 def szewl2 = "b101_1001".U 262 def szewl3 = "b101_1010".U 263 def byte2 = "b101_1011".U 264 265 def andlsb = "b110_0000".U 266 def andzexth = "b110_0001".U 267 def orlsb = "b110_0010".U 268 def orzexth = "b110_0011".U 269 def xorlsb = "b110_0100".U 270 def xorzexth = "b110_0101".U 271 def orcblsb = "b110_0110".U 272 def orcbzexth = "b110_0111".U 273 274 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 275 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 276 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 277 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 278 279 def apply() = UInt(FuOpTypeWidth.W) 280 } 281 282 object VSETOpType { 283 val setVlmaxBit = 0 284 val keepVlBit = 1 285 // destTypeBit == 0: write vl to rd 286 // destTypeBit == 1: write vconfig 287 val destTypeBit = 5 288 289 // vsetvli's uop 290 // rs1!=x0, normal 291 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 292 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 293 def uvsetvcfg_xi = "b1010_0000".U 294 def uvsetrd_xi = "b1000_0000".U 295 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 296 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 297 // uop1: w(rd) | vlmax, vtypei -> x[rd] 298 def uvsetvcfg_vlmax_i = "b1010_0001".U 299 def uvsetrd_vlmax_i = "b1000_0001".U 300 // rs1==x0, rd==x0, keep vl, set vtype 301 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 302 def uvsetvcfg_keep_v = "b1010_0010".U 303 304 // vsetvl's uop 305 // rs1!=x0, normal 306 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 307 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 308 def uvsetvcfg_xx = "b0110_0000".U 309 def uvsetrd_xx = "b0100_0000".U 310 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 311 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 312 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 313 def uvsetvcfg_vlmax_x = "b0110_0001".U 314 def uvsetrd_vlmax_x = "b0100_0001".U 315 // rs1==x0, rd==x0, keep vl, set vtype 316 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 317 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 318 def uvmv_v_x = "b0110_0010".U 319 def uvsetvcfg_vv = "b0111_0010".U 320 321 // vsetivli's uop 322 // uop0: w(vconfig) | vli, vtypei -> vconfig 323 // uop1: w(rd) | vli, vtypei -> x[rd] 324 def uvsetvcfg_ii = "b0010_0000".U 325 def uvsetrd_ii = "b0000_0000".U 326 327 def isVsetvl (func: UInt) = func(6) 328 def isVsetvli (func: UInt) = func(7) 329 def isVsetivli(func: UInt) = func(7, 6) === 0.U 330 def isNormal (func: UInt) = func(1, 0) === 0.U 331 def isSetVlmax(func: UInt) = func(setVlmaxBit) 332 def isKeepVl (func: UInt) = func(keepVlBit) 333 // RG: region 334 def writeIntRG(func: UInt) = !func(5) 335 def writeVecRG(func: UInt) = func(5) 336 def readIntRG (func: UInt) = !func(4) 337 def readVecRG (func: UInt) = func(4) 338 // modify fuOpType 339 def switchDest(func: UInt) = func ^ (1 << destTypeBit).U 340 def keepVl(func: UInt) = func | (1 << keepVlBit).U 341 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 342 } 343 344 object BRUOpType { 345 // branch 346 def beq = "b000_000".U 347 def bne = "b000_001".U 348 def blt = "b000_100".U 349 def bge = "b000_101".U 350 def bltu = "b001_000".U 351 def bgeu = "b001_001".U 352 353 def getBranchType(func: UInt) = func(3, 1) 354 def isBranchInvert(func: UInt) = func(0) 355 } 356 357 object MULOpType { 358 // mul 359 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 360 def mul = "b00000".U 361 def mulh = "b00001".U 362 def mulhsu = "b00010".U 363 def mulhu = "b00011".U 364 def mulw = "b00100".U 365 366 def mulw7 = "b01100".U 367 def isSign(op: UInt) = !op(1) 368 def isW(op: UInt) = op(2) 369 def isH(op: UInt) = op(1, 0) =/= 0.U 370 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 371 } 372 373 object DIVOpType { 374 // div 375 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 376 def div = "b10000".U 377 def divu = "b10010".U 378 def rem = "b10001".U 379 def remu = "b10011".U 380 381 def divw = "b10100".U 382 def divuw = "b10110".U 383 def remw = "b10101".U 384 def remuw = "b10111".U 385 386 def isSign(op: UInt) = !op(1) 387 def isW(op: UInt) = op(2) 388 def isH(op: UInt) = op(0) 389 } 390 391 object MDUOpType { 392 // mul 393 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 394 def mul = "b00000".U 395 def mulh = "b00001".U 396 def mulhsu = "b00010".U 397 def mulhu = "b00011".U 398 def mulw = "b00100".U 399 400 def mulw7 = "b01100".U 401 402 // div 403 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 404 def div = "b10000".U 405 def divu = "b10010".U 406 def rem = "b10001".U 407 def remu = "b10011".U 408 409 def divw = "b10100".U 410 def divuw = "b10110".U 411 def remw = "b10101".U 412 def remuw = "b10111".U 413 414 def isMul(op: UInt) = !op(4) 415 def isDiv(op: UInt) = op(4) 416 417 def isDivSign(op: UInt) = isDiv(op) && !op(1) 418 def isW(op: UInt) = op(2) 419 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 420 def getMulOp(op: UInt) = op(1, 0) 421 } 422 423 object LSUOpType { 424 // load pipeline 425 426 // normal load 427 // Note: bit(1, 0) are size, DO NOT CHANGE 428 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 429 def lb = "b0000".U 430 def lh = "b0001".U 431 def lw = "b0010".U 432 def ld = "b0011".U 433 def lbu = "b0100".U 434 def lhu = "b0101".U 435 def lwu = "b0110".U 436 437 // Zicbop software prefetch 438 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 439 def prefetch_i = "b1000".U // TODO 440 def prefetch_r = "b1001".U 441 def prefetch_w = "b1010".U 442 443 def isPrefetch(op: UInt): Bool = op(3) 444 445 // store pipeline 446 // normal store 447 // bit encoding: | store 00 | size(2bit) | 448 def sb = "b0000".U 449 def sh = "b0001".U 450 def sw = "b0010".U 451 def sd = "b0011".U 452 453 // l1 cache op 454 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 455 def cbo_zero = "b0111".U 456 457 // llc op 458 // bit encoding: | prefetch 11 | suboptype(2bit) | 459 def cbo_clean = "b1100".U 460 def cbo_flush = "b1101".U 461 def cbo_inval = "b1110".U 462 463 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 464 465 // atomics 466 // bit(1, 0) are size 467 // since atomics use a different fu type 468 // so we can safely reuse other load/store's encodings 469 // bit encoding: | optype(4bit) | size (2bit) | 470 def lr_w = "b000010".U 471 def sc_w = "b000110".U 472 def amoswap_w = "b001010".U 473 def amoadd_w = "b001110".U 474 def amoxor_w = "b010010".U 475 def amoand_w = "b010110".U 476 def amoor_w = "b011010".U 477 def amomin_w = "b011110".U 478 def amomax_w = "b100010".U 479 def amominu_w = "b100110".U 480 def amomaxu_w = "b101010".U 481 482 def lr_d = "b000011".U 483 def sc_d = "b000111".U 484 def amoswap_d = "b001011".U 485 def amoadd_d = "b001111".U 486 def amoxor_d = "b010011".U 487 def amoand_d = "b010111".U 488 def amoor_d = "b011011".U 489 def amomin_d = "b011111".U 490 def amomax_d = "b100011".U 491 def amominu_d = "b100111".U 492 def amomaxu_d = "b101011".U 493 494 def size(op: UInt) = op(1,0) 495 } 496 497 object BKUOpType { 498 499 def clmul = "b000000".U 500 def clmulh = "b000001".U 501 def clmulr = "b000010".U 502 def xpermn = "b000100".U 503 def xpermb = "b000101".U 504 505 def clz = "b001000".U 506 def clzw = "b001001".U 507 def ctz = "b001010".U 508 def ctzw = "b001011".U 509 def cpop = "b001100".U 510 def cpopw = "b001101".U 511 512 // 01xxxx is reserve 513 def aes64es = "b100000".U 514 def aes64esm = "b100001".U 515 def aes64ds = "b100010".U 516 def aes64dsm = "b100011".U 517 def aes64im = "b100100".U 518 def aes64ks1i = "b100101".U 519 def aes64ks2 = "b100110".U 520 521 // merge to two instruction sm4ks & sm4ed 522 def sm4ed0 = "b101000".U 523 def sm4ed1 = "b101001".U 524 def sm4ed2 = "b101010".U 525 def sm4ed3 = "b101011".U 526 def sm4ks0 = "b101100".U 527 def sm4ks1 = "b101101".U 528 def sm4ks2 = "b101110".U 529 def sm4ks3 = "b101111".U 530 531 def sha256sum0 = "b110000".U 532 def sha256sum1 = "b110001".U 533 def sha256sig0 = "b110010".U 534 def sha256sig1 = "b110011".U 535 def sha512sum0 = "b110100".U 536 def sha512sum1 = "b110101".U 537 def sha512sig0 = "b110110".U 538 def sha512sig1 = "b110111".U 539 540 def sm3p0 = "b111000".U 541 def sm3p1 = "b111001".U 542 } 543 544 object BTBtype { 545 def B = "b00".U // branch 546 def J = "b01".U // jump 547 def I = "b10".U // indirect 548 def R = "b11".U // return 549 550 def apply() = UInt(2.W) 551 } 552 553 object SelImm { 554 def IMM_X = "b0111".U 555 def IMM_S = "b1110".U 556 def IMM_SB = "b0001".U 557 def IMM_U = "b0010".U 558 def IMM_UJ = "b0011".U 559 def IMM_I = "b0100".U 560 def IMM_Z = "b0101".U 561 def INVALID_INSTR = "b0110".U 562 def IMM_B6 = "b1000".U 563 564 def IMM_OPIVIS = "b1001".U 565 def IMM_OPIVIU = "b1010".U 566 def IMM_VSETVLI = "b1100".U 567 def IMM_VSETIVLI = "b1101".U 568 def IMM_LUI32 = "b1011".U 569 570 def X = BitPat("b0000") 571 572 def apply() = UInt(4.W) 573 574 def mkString(immType: UInt) : String = { 575 val strMap = Map( 576 IMM_S.litValue -> "S", 577 IMM_SB.litValue -> "SB", 578 IMM_U.litValue -> "U", 579 IMM_UJ.litValue -> "UJ", 580 IMM_I.litValue -> "I", 581 IMM_Z.litValue -> "Z", 582 IMM_B6.litValue -> "B6", 583 IMM_OPIVIS.litValue -> "VIS", 584 IMM_OPIVIU.litValue -> "VIU", 585 IMM_VSETVLI.litValue -> "VSETVLI", 586 IMM_VSETIVLI.litValue -> "VSETIVLI", 587 IMM_LUI32.litValue -> "LUI32", 588 INVALID_INSTR.litValue -> "INVALID", 589 ) 590 strMap(immType.litValue) 591 } 592 } 593 594 object UopSplitType { 595 def SCA_SIM = "b000000".U // 596 def DIR = "b010001".U // dirty: vset 597 def VEC_VVV = "b010010".U // VEC_VVV 598 def VEC_VXV = "b010011".U // VEC_VXV 599 def VEC_0XV = "b010100".U // VEC_0XV 600 def VEC_VVW = "b010101".U // VEC_VVW 601 def VEC_WVW = "b010110".U // VEC_WVW 602 def VEC_VXW = "b010111".U // VEC_VXW 603 def VEC_WXW = "b011000".U // VEC_WXW 604 def VEC_WVV = "b011001".U // VEC_WVV 605 def VEC_WXV = "b011010".U // VEC_WXV 606 def VEC_EXT2 = "b011011".U // VF2 0 -> V 607 def VEC_EXT4 = "b011100".U // VF4 0 -> V 608 def VEC_EXT8 = "b011101".U // VF8 0 -> V 609 def VEC_VVM = "b011110".U // VEC_VVM 610 def VEC_VXM = "b011111".U // VEC_VXM 611 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 612 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 613 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 614 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 615 def VEC_VRED = "b100100".U // VEC_VRED 616 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 617 def VEC_ISLIDEUP = "b100110".U // VEC_ISLIDEUP 618 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 619 def VEC_ISLIDEDOWN = "b101000".U // VEC_ISLIDEDOWN 620 def VEC_M0X = "b101001".U // VEC_M0X 0MV 621 def VEC_MVV = "b101010".U // VEC_MVV VMV 622 def VEC_M0X_VFIRST = "b101011".U // 623 def VEC_VWW = "b101100".U // 624 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 625 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 626 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 627 def VEC_COMPRESS = "b110000".U // vcompress.vm 628 def VEC_US_LD = "b110001".U // vector unit strided load 629 def VEC_VFV = "b111000".U // VEC_VFV 630 def VEC_VFW = "b111001".U // VEC_VFW 631 def VEC_WFW = "b111010".U // VEC_WVW 632 def VEC_VFM = "b111011".U // VEC_VFM 633 def VEC_VFRED = "b111100".U // VEC_VFRED 634 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 635 def VEC_M0M = "b000000".U // VEC_M0M 636 def VEC_MMM = "b000000".U // VEC_MMM 637 def dummy = "b111111".U 638 639 def X = BitPat("b000000") 640 641 def apply() = UInt(6.W) 642 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 643 } 644 645 object ExceptionNO { 646 def instrAddrMisaligned = 0 647 def instrAccessFault = 1 648 def illegalInstr = 2 649 def breakPoint = 3 650 def loadAddrMisaligned = 4 651 def loadAccessFault = 5 652 def storeAddrMisaligned = 6 653 def storeAccessFault = 7 654 def ecallU = 8 655 def ecallS = 9 656 def ecallM = 11 657 def instrPageFault = 12 658 def loadPageFault = 13 659 // def singleStep = 14 660 def storePageFault = 15 661 def priorities = Seq( 662 breakPoint, // TODO: different BP has different priority 663 instrPageFault, 664 instrAccessFault, 665 illegalInstr, 666 instrAddrMisaligned, 667 ecallM, ecallS, ecallU, 668 storeAddrMisaligned, 669 loadAddrMisaligned, 670 storePageFault, 671 loadPageFault, 672 storeAccessFault, 673 loadAccessFault 674 ) 675 def all = priorities.distinct.sorted 676 def frontendSet = Seq( 677 instrAddrMisaligned, 678 instrAccessFault, 679 illegalInstr, 680 instrPageFault 681 ) 682 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 683 val new_vec = Wire(ExceptionVec()) 684 new_vec.foreach(_ := false.B) 685 select.foreach(i => new_vec(i) := vec(i)) 686 new_vec 687 } 688 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 689 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 690 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 691 partialSelect(vec, fuConfig.exceptionOut) 692 } 693 694 // indicates where the memory access request comes from 695 // a dupliacte of this is in HuanCun.common and CoupledL2.common 696 // TODO: consider moving it to Utility, so that they could share the same definition 697 object MemReqSource extends Enumeration { 698 val NoWhere = Value("NoWhere") 699 700 val CPUInst = Value("CPUInst") 701 val CPULoadData = Value("CPULoadData") 702 val CPUStoreData = Value("CPUStoreData") 703 val CPUAtomicData = Value("CPUAtomicData") 704 val L1InstPrefetch = Value("L1InstPrefetch") 705 val L1DataPrefetch = Value("L1DataPrefetch") 706 val PTW = Value("PTW") 707 val L2Prefetch = Value("L2Prefetch") 708 val ReqSourceCount = Value("ReqSourceCount") 709 710 val reqSourceBits = log2Ceil(ReqSourceCount.id) 711 } 712 713 object TopDownCounters extends Enumeration { 714 val NoStall = Value("NoStall") // Base 715 // frontend 716 val OverrideBubble = Value("OverrideBubble") 717 val FtqUpdateBubble = Value("FtqUpdateBubble") 718 // val ControlRedirectBubble = Value("ControlRedirectBubble") 719 val TAGEMissBubble = Value("TAGEMissBubble") 720 val SCMissBubble = Value("SCMissBubble") 721 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 722 val RASMissBubble = Value("RASMissBubble") 723 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 724 val OtherRedirectBubble = Value("OtherRedirectBubble") 725 val FtqFullStall = Value("FtqFullStall") 726 727 val ICacheMissBubble = Value("ICacheMissBubble") 728 val ITLBMissBubble = Value("ITLBMissBubble") 729 val BTBMissBubble = Value("BTBMissBubble") 730 val FetchFragBubble = Value("FetchFragBubble") 731 732 // backend 733 // long inst stall at rob head 734 val DivStall = Value("DivStall") // int div, float div/sqrt 735 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 736 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 737 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 738 // freelist full 739 val IntFlStall = Value("IntFlStall") 740 val FpFlStall = Value("FpFlStall") 741 // dispatch queue full 742 val IntDqStall = Value("IntDqStall") 743 val FpDqStall = Value("FpDqStall") 744 val LsDqStall = Value("LsDqStall") 745 746 // memblock 747 val LoadTLBStall = Value("LoadTLBStall") 748 val LoadL1Stall = Value("LoadL1Stall") 749 val LoadL2Stall = Value("LoadL2Stall") 750 val LoadL3Stall = Value("LoadL3Stall") 751 val LoadMemStall = Value("LoadMemStall") 752 val StoreStall = Value("StoreStall") // include store tlb miss 753 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 754 755 // xs replay (different to gem5) 756 val LoadVioReplayStall = Value("LoadVioReplayStall") 757 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 758 759 // bad speculation 760 val ControlRecoveryStall = Value("ControlRecoveryStall") 761 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 762 val OtherRecoveryStall = Value("OtherRecoveryStall") 763 764 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 765 766 val OtherCoreStall = Value("OtherCoreStall") 767 768 val NumStallReasons = Value("NumStallReasons") 769 } 770} 771