1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 def no = "b000".U // this src read no reg but cannot be Any value 36 37 // alias 38 def reg = this.xp 39 def DC = imm // Don't Care 40 def X = BitPat("b000") 41 42 def isPc(srcType: UInt) = srcType===pc 43 def isImm(srcType: UInt) = srcType===imm 44 def isReg(srcType: UInt) = srcType(0) 45 def isXp(srcType: UInt) = srcType(0) 46 def isFp(srcType: UInt) = srcType(1) 47 def isVp(srcType: UInt) = srcType(2) 48 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 49 def isNotReg(srcType: UInt): Bool = !srcType.orR 50 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 51 def apply() = UInt(3.W) 52 } 53 54 object SrcState { 55 def busy = "b0".U 56 def rdy = "b1".U 57 // def specRdy = "b10".U // speculative ready, for future use 58 def apply() = UInt(1.W) 59 60 def isReady(state: UInt): Bool = state === this.rdy 61 def isBusy(state: UInt): Bool = state === this.busy 62 } 63 64 def FuOpTypeWidth = 9 65 object FuOpType { 66 def apply() = UInt(FuOpTypeWidth.W) 67 def X = BitPat("b00000000") 68 } 69 70 object VlduType { 71 // bit encoding: | padding (2bit) || mop (2bit) | lumop(5bit) | 72 // only unit-stride use lumop 73 // mop [1:0] 74 // 0 0 : unit-stride 75 // 0 1 : indexed-unordered 76 // 1 0 : strided 77 // 1 1 : indexed-ordered 78 // lumop[4:0] 79 // 0 0 0 0 0 : unit-stride load 80 // 0 1 0 0 0 : unit-stride, whole register load 81 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 82 // 1 0 0 0 0 : unit-stride fault-only-first 83 def vle = "b00_00_00000".U 84 def vlr = "b00_00_01000".U 85 def vlm = "b00_00_01011".U 86 def vleff = "b00_00_10000".U 87 def vluxe = "b00_01_00000".U 88 def vlse = "b00_10_00000".U 89 def vloxe = "b00_11_00000".U 90 91 def isStrided(fuOpType: UInt): Bool = fuOpType === vlse 92 def isIndexed(fuOpType: UInt): Bool = fuOpType === vluxe || fuOpType === vloxe 93 } 94 95 object VstuType { 96 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 97 // only unit-stride use sumop 98 // mop [1:0] 99 // 0 0 : unit-stride 100 // 0 1 : indexed-unordered 101 // 1 0 : strided 102 // 1 1 : indexed-ordered 103 // sumop[4:0] 104 // 0 0 0 0 0 : unit-stride load 105 // 0 1 0 0 0 : unit-stride, whole register load 106 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 107 def vse = "b00_00_00000".U 108 def vsr = "b00_00_01000".U 109 def vsm = "b00_00_01011".U 110 def vsuxe = "b00_01_00000".U 111 def vsse = "b00_10_00000".U 112 def vsoxe = "b00_11_00000".U 113 114 def isStrided(fuOpType: UInt): Bool = fuOpType === vsse 115 def isIndexed(fuOpType: UInt): Bool = fuOpType === vsuxe || fuOpType === vsoxe 116 } 117 118 object IF2VectorType { 119 // use last 3 bits for vsew 120 def i2vector = "b00_00".U 121 def f2vector = "b00_01".U 122 def imm2vector = "b00_10".U 123 def permImm2vector = "b00_11".U 124 } 125 126 object CommitType { 127 def NORMAL = "b000".U // int/fp 128 def BRANCH = "b001".U // branch 129 def LOAD = "b010".U // load 130 def STORE = "b011".U // store 131 132 def apply() = UInt(3.W) 133 def isFused(commitType: UInt): Bool = commitType(2) 134 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 135 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 136 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 137 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 138 } 139 140 object RedirectLevel { 141 def flushAfter = "b0".U 142 def flush = "b1".U 143 144 def apply() = UInt(1.W) 145 // def isUnconditional(level: UInt) = level(1) 146 def flushItself(level: UInt) = level(0) 147 // def isException(level: UInt) = level(1) && level(0) 148 } 149 150 object ExceptionVec { 151 val ExceptionVecSize = 16 152 def apply() = Vec(ExceptionVecSize, Bool()) 153 } 154 155 object PMAMode { 156 def R = "b1".U << 0 //readable 157 def W = "b1".U << 1 //writeable 158 def X = "b1".U << 2 //executable 159 def I = "b1".U << 3 //cacheable: icache 160 def D = "b1".U << 4 //cacheable: dcache 161 def S = "b1".U << 5 //enable speculative access 162 def A = "b1".U << 6 //enable atomic operation, A imply R & W 163 def C = "b1".U << 7 //if it is cacheable is configable 164 def Reserved = "b0".U 165 166 def apply() = UInt(7.W) 167 168 def read(mode: UInt) = mode(0) 169 def write(mode: UInt) = mode(1) 170 def execute(mode: UInt) = mode(2) 171 def icache(mode: UInt) = mode(3) 172 def dcache(mode: UInt) = mode(4) 173 def speculate(mode: UInt) = mode(5) 174 def atomic(mode: UInt) = mode(6) 175 def configable_cache(mode: UInt) = mode(7) 176 177 def strToMode(s: String) = { 178 var result = 0.U(8.W) 179 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 180 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 181 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 182 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 183 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 184 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 185 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 186 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 187 result 188 } 189 } 190 191 192 object CSROpType { 193 def jmp = "b000".U 194 def wrt = "b001".U 195 def set = "b010".U 196 def clr = "b011".U 197 def wfi = "b100".U 198 def wrti = "b101".U 199 def seti = "b110".U 200 def clri = "b111".U 201 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 202 } 203 204 // jump 205 object JumpOpType { 206 def jal = "b00".U 207 def jalr = "b01".U 208 def auipc = "b10".U 209// def call = "b11_011".U 210// def ret = "b11_100".U 211 def jumpOpisJalr(op: UInt) = op(0) 212 def jumpOpisAuipc(op: UInt) = op(1) 213 } 214 215 object FenceOpType { 216 def fence = "b10000".U 217 def sfence = "b10001".U 218 def fencei = "b10010".U 219 def nofence= "b00000".U 220 } 221 222 object ALUOpType { 223 // shift optype 224 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 225 def sll = "b000_0001".U // sll: src1 << src2 226 227 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 228 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 229 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 230 231 def srl = "b000_0101".U // srl: src1 >> src2 232 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 233 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 234 235 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 236 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 237 238 // RV64 32bit optype 239 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 240 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 241 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 242 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 243 244 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 245 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 246 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 247 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 248 249 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 250 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 251 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 252 def rolw = "b001_1100".U 253 def rorw = "b001_1101".U 254 255 // ADD-op 256 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 257 def add = "b010_0001".U // add: src1 + src2 258 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 259 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 260 261 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 262 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 263 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 264 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 265 266 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 267 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 268 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 269 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 270 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 271 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 272 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 273 274 // SUB-op: src1 - src2 275 def sub = "b011_0000".U 276 def sltu = "b011_0001".U 277 def slt = "b011_0010".U 278 def maxu = "b011_0100".U 279 def minu = "b011_0101".U 280 def max = "b011_0110".U 281 def min = "b011_0111".U 282 283 // branch 284 def beq = "b111_0000".U 285 def bne = "b111_0010".U 286 def blt = "b111_1000".U 287 def bge = "b111_1010".U 288 def bltu = "b111_1100".U 289 def bgeu = "b111_1110".U 290 291 // misc optype 292 def and = "b100_0000".U 293 def andn = "b100_0001".U 294 def or = "b100_0010".U 295 def orn = "b100_0011".U 296 def xor = "b100_0100".U 297 def xnor = "b100_0101".U 298 def orcb = "b100_0110".U 299 300 def sextb = "b100_1000".U 301 def packh = "b100_1001".U 302 def sexth = "b100_1010".U 303 def packw = "b100_1011".U 304 305 def revb = "b101_0000".U 306 def rev8 = "b101_0001".U 307 def pack = "b101_0010".U 308 def orh48 = "b101_0011".U 309 310 def szewl1 = "b101_1000".U 311 def szewl2 = "b101_1001".U 312 def szewl3 = "b101_1010".U 313 def byte2 = "b101_1011".U 314 315 def andlsb = "b110_0000".U 316 def andzexth = "b110_0001".U 317 def orlsb = "b110_0010".U 318 def orzexth = "b110_0011".U 319 def xorlsb = "b110_0100".U 320 def xorzexth = "b110_0101".U 321 def orcblsb = "b110_0110".U 322 def orcbzexth = "b110_0111".U 323 324 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 325 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 326 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 327 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 328 329 def apply() = UInt(FuOpTypeWidth.W) 330 } 331 332 object VSETOpType { 333 val setVlmaxBit = 0 334 val keepVlBit = 1 335 // destTypeBit == 0: write vl to rd 336 // destTypeBit == 1: write vconfig 337 val destTypeBit = 5 338 339 // vsetvli's uop 340 // rs1!=x0, normal 341 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 342 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 343 def uvsetvcfg_xi = "b1010_0000".U 344 def uvsetrd_xi = "b1000_0000".U 345 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 346 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 347 // uop1: w(rd) | vlmax, vtypei -> x[rd] 348 def uvsetvcfg_vlmax_i = "b1010_0001".U 349 def uvsetrd_vlmax_i = "b1000_0001".U 350 // rs1==x0, rd==x0, keep vl, set vtype 351 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 352 def uvsetvcfg_keep_v = "b1010_0010".U 353 354 // vsetvl's uop 355 // rs1!=x0, normal 356 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 357 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 358 def uvsetvcfg_xx = "b0110_0000".U 359 def uvsetrd_xx = "b0100_0000".U 360 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 361 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 362 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 363 def uvsetvcfg_vlmax_x = "b0110_0001".U 364 def uvsetrd_vlmax_x = "b0100_0001".U 365 // rs1==x0, rd==x0, keep vl, set vtype 366 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 367 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 368 def uvmv_v_x = "b0110_0010".U 369 def uvsetvcfg_vv = "b0111_0010".U 370 371 // vsetivli's uop 372 // uop0: w(vconfig) | vli, vtypei -> vconfig 373 // uop1: w(rd) | vli, vtypei -> x[rd] 374 def uvsetvcfg_ii = "b0010_0000".U 375 def uvsetrd_ii = "b0000_0000".U 376 377 def isVsetvl (func: UInt) = func(6) 378 def isVsetvli (func: UInt) = func(7) 379 def isVsetivli(func: UInt) = func(7, 6) === 0.U 380 def isNormal (func: UInt) = func(1, 0) === 0.U 381 def isSetVlmax(func: UInt) = func(setVlmaxBit) 382 def isKeepVl (func: UInt) = func(keepVlBit) 383 // RG: region 384 def writeIntRG(func: UInt) = !func(5) 385 def writeVecRG(func: UInt) = func(5) 386 def readIntRG (func: UInt) = !func(4) 387 def readVecRG (func: UInt) = func(4) 388 // modify fuOpType 389 def keepVl(func: UInt) = func | (1 << keepVlBit).U 390 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 391 } 392 393 object BRUOpType { 394 // branch 395 def beq = "b000_000".U 396 def bne = "b000_001".U 397 def blt = "b000_100".U 398 def bge = "b000_101".U 399 def bltu = "b001_000".U 400 def bgeu = "b001_001".U 401 402 def getBranchType(func: UInt) = func(3, 1) 403 def isBranchInvert(func: UInt) = func(0) 404 } 405 406 object MULOpType { 407 // mul 408 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 409 def mul = "b00000".U 410 def mulh = "b00001".U 411 def mulhsu = "b00010".U 412 def mulhu = "b00011".U 413 def mulw = "b00100".U 414 415 def mulw7 = "b01100".U 416 def isSign(op: UInt) = !op(1) 417 def isW(op: UInt) = op(2) 418 def isH(op: UInt) = op(1, 0) =/= 0.U 419 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 420 } 421 422 object DIVOpType { 423 // div 424 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 425 def div = "b10000".U 426 def divu = "b10010".U 427 def rem = "b10001".U 428 def remu = "b10011".U 429 430 def divw = "b10100".U 431 def divuw = "b10110".U 432 def remw = "b10101".U 433 def remuw = "b10111".U 434 435 def isSign(op: UInt) = !op(1) 436 def isW(op: UInt) = op(2) 437 def isH(op: UInt) = op(0) 438 } 439 440 object MDUOpType { 441 // mul 442 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 443 def mul = "b00000".U 444 def mulh = "b00001".U 445 def mulhsu = "b00010".U 446 def mulhu = "b00011".U 447 def mulw = "b00100".U 448 449 def mulw7 = "b01100".U 450 451 // div 452 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 453 def div = "b10000".U 454 def divu = "b10010".U 455 def rem = "b10001".U 456 def remu = "b10011".U 457 458 def divw = "b10100".U 459 def divuw = "b10110".U 460 def remw = "b10101".U 461 def remuw = "b10111".U 462 463 def isMul(op: UInt) = !op(4) 464 def isDiv(op: UInt) = op(4) 465 466 def isDivSign(op: UInt) = isDiv(op) && !op(1) 467 def isW(op: UInt) = op(2) 468 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 469 def getMulOp(op: UInt) = op(1, 0) 470 } 471 472 object LSUOpType { 473 // load pipeline 474 475 // normal load 476 // Note: bit(1, 0) are size, DO NOT CHANGE 477 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 478 def lb = "b0000".U 479 def lh = "b0001".U 480 def lw = "b0010".U 481 def ld = "b0011".U 482 def lbu = "b0100".U 483 def lhu = "b0101".U 484 def lwu = "b0110".U 485 486 // Zicbop software prefetch 487 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 488 def prefetch_i = "b1000".U // TODO 489 def prefetch_r = "b1001".U 490 def prefetch_w = "b1010".U 491 492 def isPrefetch(op: UInt): Bool = op(3) 493 494 // store pipeline 495 // normal store 496 // bit encoding: | store 00 | size(2bit) | 497 def sb = "b0000".U 498 def sh = "b0001".U 499 def sw = "b0010".U 500 def sd = "b0011".U 501 502 // l1 cache op 503 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 504 def cbo_zero = "b0111".U 505 506 // llc op 507 // bit encoding: | prefetch 11 | suboptype(2bit) | 508 def cbo_clean = "b1100".U 509 def cbo_flush = "b1101".U 510 def cbo_inval = "b1110".U 511 512 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 513 514 // atomics 515 // bit(1, 0) are size 516 // since atomics use a different fu type 517 // so we can safely reuse other load/store's encodings 518 // bit encoding: | optype(4bit) | size (2bit) | 519 def lr_w = "b000010".U 520 def sc_w = "b000110".U 521 def amoswap_w = "b001010".U 522 def amoadd_w = "b001110".U 523 def amoxor_w = "b010010".U 524 def amoand_w = "b010110".U 525 def amoor_w = "b011010".U 526 def amomin_w = "b011110".U 527 def amomax_w = "b100010".U 528 def amominu_w = "b100110".U 529 def amomaxu_w = "b101010".U 530 531 def lr_d = "b000011".U 532 def sc_d = "b000111".U 533 def amoswap_d = "b001011".U 534 def amoadd_d = "b001111".U 535 def amoxor_d = "b010011".U 536 def amoand_d = "b010111".U 537 def amoor_d = "b011011".U 538 def amomin_d = "b011111".U 539 def amomax_d = "b100011".U 540 def amominu_d = "b100111".U 541 def amomaxu_d = "b101011".U 542 543 def size(op: UInt) = op(1,0) 544 } 545 546 object BKUOpType { 547 548 def clmul = "b000000".U 549 def clmulh = "b000001".U 550 def clmulr = "b000010".U 551 def xpermn = "b000100".U 552 def xpermb = "b000101".U 553 554 def clz = "b001000".U 555 def clzw = "b001001".U 556 def ctz = "b001010".U 557 def ctzw = "b001011".U 558 def cpop = "b001100".U 559 def cpopw = "b001101".U 560 561 // 01xxxx is reserve 562 def aes64es = "b100000".U 563 def aes64esm = "b100001".U 564 def aes64ds = "b100010".U 565 def aes64dsm = "b100011".U 566 def aes64im = "b100100".U 567 def aes64ks1i = "b100101".U 568 def aes64ks2 = "b100110".U 569 570 // merge to two instruction sm4ks & sm4ed 571 def sm4ed0 = "b101000".U 572 def sm4ed1 = "b101001".U 573 def sm4ed2 = "b101010".U 574 def sm4ed3 = "b101011".U 575 def sm4ks0 = "b101100".U 576 def sm4ks1 = "b101101".U 577 def sm4ks2 = "b101110".U 578 def sm4ks3 = "b101111".U 579 580 def sha256sum0 = "b110000".U 581 def sha256sum1 = "b110001".U 582 def sha256sig0 = "b110010".U 583 def sha256sig1 = "b110011".U 584 def sha512sum0 = "b110100".U 585 def sha512sum1 = "b110101".U 586 def sha512sig0 = "b110110".U 587 def sha512sig1 = "b110111".U 588 589 def sm3p0 = "b111000".U 590 def sm3p1 = "b111001".U 591 } 592 593 object BTBtype { 594 def B = "b00".U // branch 595 def J = "b01".U // jump 596 def I = "b10".U // indirect 597 def R = "b11".U // return 598 599 def apply() = UInt(2.W) 600 } 601 602 object SelImm { 603 def IMM_X = "b0111".U 604 def IMM_S = "b1110".U 605 def IMM_SB = "b0001".U 606 def IMM_U = "b0010".U 607 def IMM_UJ = "b0011".U 608 def IMM_I = "b0100".U 609 def IMM_Z = "b0101".U 610 def INVALID_INSTR = "b0110".U 611 def IMM_B6 = "b1000".U 612 613 def IMM_OPIVIS = "b1001".U 614 def IMM_OPIVIU = "b1010".U 615 def IMM_VSETVLI = "b1100".U 616 def IMM_VSETIVLI = "b1101".U 617 def IMM_LUI32 = "b1011".U 618 619 def X = BitPat("b0000") 620 621 def apply() = UInt(4.W) 622 623 def mkString(immType: UInt) : String = { 624 val strMap = Map( 625 IMM_S.litValue -> "S", 626 IMM_SB.litValue -> "SB", 627 IMM_U.litValue -> "U", 628 IMM_UJ.litValue -> "UJ", 629 IMM_I.litValue -> "I", 630 IMM_Z.litValue -> "Z", 631 IMM_B6.litValue -> "B6", 632 IMM_OPIVIS.litValue -> "VIS", 633 IMM_OPIVIU.litValue -> "VIU", 634 IMM_VSETVLI.litValue -> "VSETVLI", 635 IMM_VSETIVLI.litValue -> "VSETIVLI", 636 IMM_LUI32.litValue -> "LUI32", 637 INVALID_INSTR.litValue -> "INVALID", 638 ) 639 strMap(immType.litValue) 640 } 641 } 642 643 object UopSplitType { 644 def SCA_SIM = "b000000".U // 645 def VSET = "b010001".U // dirty: vset 646 def VEC_VVV = "b010010".U // VEC_VVV 647 def VEC_VXV = "b010011".U // VEC_VXV 648 def VEC_0XV = "b010100".U // VEC_0XV 649 def VEC_VVW = "b010101".U // VEC_VVW 650 def VEC_WVW = "b010110".U // VEC_WVW 651 def VEC_VXW = "b010111".U // VEC_VXW 652 def VEC_WXW = "b011000".U // VEC_WXW 653 def VEC_WVV = "b011001".U // VEC_WVV 654 def VEC_WXV = "b011010".U // VEC_WXV 655 def VEC_EXT2 = "b011011".U // VF2 0 -> V 656 def VEC_EXT4 = "b011100".U // VF4 0 -> V 657 def VEC_EXT8 = "b011101".U // VF8 0 -> V 658 def VEC_VVM = "b011110".U // VEC_VVM 659 def VEC_VXM = "b011111".U // VEC_VXM 660 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 661 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 662 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 663 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 664 def VEC_VRED = "b100100".U // VEC_VRED 665 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 666 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 667 def VEC_M0X = "b101001".U // VEC_M0X 0MV 668 def VEC_MVV = "b101010".U // VEC_MVV VMV 669 def VEC_M0X_VFIRST = "b101011".U // 670 def VEC_VWW = "b101100".U // 671 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 672 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 673 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 674 def VEC_COMPRESS = "b110000".U // vcompress.vm 675 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 676 def VEC_S_LDST = "b110010".U // vector strided load/store 677 def VEC_I_LDST = "b110011".U // vector indexed load/store 678 def VEC_VFV = "b111000".U // VEC_VFV 679 def VEC_VFW = "b111001".U // VEC_VFW 680 def VEC_WFW = "b111010".U // VEC_WVW 681 def VEC_VFM = "b111011".U // VEC_VFM 682 def VEC_VFRED = "b111100".U // VEC_VFRED 683 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 684 def VEC_M0M = "b000000".U // VEC_M0M 685 def VEC_MMM = "b000000".U // VEC_MMM 686 def VEC_MVNR = "b000100".U // vmvnr 687 def dummy = "b111111".U 688 689 def X = BitPat("b000000") 690 691 def apply() = UInt(6.W) 692 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 693 } 694 695 object ExceptionNO { 696 def instrAddrMisaligned = 0 697 def instrAccessFault = 1 698 def illegalInstr = 2 699 def breakPoint = 3 700 def loadAddrMisaligned = 4 701 def loadAccessFault = 5 702 def storeAddrMisaligned = 6 703 def storeAccessFault = 7 704 def ecallU = 8 705 def ecallS = 9 706 def ecallM = 11 707 def instrPageFault = 12 708 def loadPageFault = 13 709 // def singleStep = 14 710 def storePageFault = 15 711 def priorities = Seq( 712 breakPoint, // TODO: different BP has different priority 713 instrPageFault, 714 instrAccessFault, 715 illegalInstr, 716 instrAddrMisaligned, 717 ecallM, ecallS, ecallU, 718 storeAddrMisaligned, 719 loadAddrMisaligned, 720 storePageFault, 721 loadPageFault, 722 storeAccessFault, 723 loadAccessFault 724 ) 725 def all = priorities.distinct.sorted 726 def frontendSet = Seq( 727 instrAddrMisaligned, 728 instrAccessFault, 729 illegalInstr, 730 instrPageFault 731 ) 732 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 733 val new_vec = Wire(ExceptionVec()) 734 new_vec.foreach(_ := false.B) 735 select.foreach(i => new_vec(i) := vec(i)) 736 new_vec 737 } 738 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 739 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 740 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 741 partialSelect(vec, fuConfig.exceptionOut) 742 } 743 744 object TopDownCounters extends Enumeration { 745 val NoStall = Value("NoStall") // Base 746 // frontend 747 val OverrideBubble = Value("OverrideBubble") 748 val FtqUpdateBubble = Value("FtqUpdateBubble") 749 // val ControlRedirectBubble = Value("ControlRedirectBubble") 750 val TAGEMissBubble = Value("TAGEMissBubble") 751 val SCMissBubble = Value("SCMissBubble") 752 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 753 val RASMissBubble = Value("RASMissBubble") 754 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 755 val OtherRedirectBubble = Value("OtherRedirectBubble") 756 val FtqFullStall = Value("FtqFullStall") 757 758 val ICacheMissBubble = Value("ICacheMissBubble") 759 val ITLBMissBubble = Value("ITLBMissBubble") 760 val BTBMissBubble = Value("BTBMissBubble") 761 val FetchFragBubble = Value("FetchFragBubble") 762 763 // backend 764 // long inst stall at rob head 765 val DivStall = Value("DivStall") // int div, float div/sqrt 766 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 767 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 768 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 769 // freelist full 770 val IntFlStall = Value("IntFlStall") 771 val FpFlStall = Value("FpFlStall") 772 // dispatch queue full 773 val IntDqStall = Value("IntDqStall") 774 val FpDqStall = Value("FpDqStall") 775 val LsDqStall = Value("LsDqStall") 776 777 // memblock 778 val LoadTLBStall = Value("LoadTLBStall") 779 val LoadL1Stall = Value("LoadL1Stall") 780 val LoadL2Stall = Value("LoadL2Stall") 781 val LoadL3Stall = Value("LoadL3Stall") 782 val LoadMemStall = Value("LoadMemStall") 783 val StoreStall = Value("StoreStall") // include store tlb miss 784 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 785 786 // xs replay (different to gem5) 787 val LoadVioReplayStall = Value("LoadVioReplayStall") 788 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 789 790 // bad speculation 791 val ControlRecoveryStall = Value("ControlRecoveryStall") 792 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 793 val OtherRecoveryStall = Value("OtherRecoveryStall") 794 795 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 796 797 val OtherCoreStall = Value("OtherCoreStall") 798 799 val NumStallReasons = Value("NumStallReasons") 800 } 801} 802