fix(Zicclsm): Vectors should not support misaligned access by Hardware (#3460)

In the current design, do not let vector instructions do hardware
misaligned.

Remove `RVA23` prefix and enable CMO by default (#3431)

+ Remove `RVA23` prefix to clean up code
+ set `hasCMO` to true by default

LoadQueueReplay: fix LoadQueueReplay enqueue logic (#3436)

LoadQueueReplay can always enter, as long as it is the same size as
VirtualLoadQueue.

zfhmin:add zfhmin extensions

*decode unit adds decoding of zfhmin extension related instructions
*Re exemplified the functional units for scalar fpcvt

RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
-

RVA23 CMO (Cache Maintenance Operation) (#3426)

Supports Zicbom Extension (Clean/Flush/Invalid)
- https://github.com/OpenXiangShan/CoupledL2/pull/225

This PR also includes other CPL2 changes:
- bug fixes
- timing fixes
- SRAM-Queue | https://github.com/OpenXiangShan/CoupledL2/pull/228
- data SRAM splitted into 4 |
https://github.com/OpenXiangShan/CoupledL2/pull/229

---------

Co-authored-by: lixin <[email protected]>

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RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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StoreQueue: do not submit inactive vector store to sbuffer (#3350)

We cannot set vecValid when mask is all 0.

LoadQueueRAW: need check only when storeIn is valid

* If storeIn is not valid, the bits in storeIn means nothing. Using bits when valid is not asserted will cause X propagation.

StoreQueue: remove useless path of vector store mmio

LoadUnit: refactor writeback data select logic

Uncachebuffer: valid and bits of redirect should be seperately regenabled (#3274)

LSQ: optimize static clock gating coverage and fix x_value in vcs (#3176)

optimize LSQ static clock gating coverage, fix x_value in vcs

build: purge chisel 3 and add deprecation check (#3250)

MemBlock: refactor selectOldest of rollback for better timing

Don't select oldest rollback twice in LoadQueueRAW, send to memblock select oldest with other, will have port to send rollback request

MemBlock: refactor selectOldest of rollback for better timing

Don't select oldest rollback twice in LoadQueueRAW, send to memblock select oldest with other, will have port to send rollback request to memblock in LoadQueueRAW.

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VLSU: fix bugs related to vector access exceptions (#3169)

fix the bug of vector unit-stride exception address calculation

fix connection between vector exception and 'exceptionBuffer' in 'LoadQu

VLSU: fix bugs related to vector access exceptions (#3169)

fix the bug of vector unit-stride exception address calculation

fix connection between vector exception and 'exceptionBuffer' in 'LoadQueue'

At present, the vector access exception processing still needs to wait
for the modification of the back-end. We will test after the back-end is
completed, and may also adapt the storage access side.

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StoreQueue: Change timeout to an existing API(TimeOutAssert) implementation.

StoreQueue: fix exception entry mistakenly written to sbuffer (#3119)

StoreQueue: Add exception handling logic for vector instructions.

All vector instruction uop normally dequeue, but the Uop after the exception is raised does not write to the 'sbuffer'.
Flags are us

StoreQueue: Add exception handling logic for vector instructions.

All vector instruction uop normally dequeue, but the Uop after the exception is raised does not write to the 'sbuffer'.
Flags are used to record whether there are any exceptions when the queue is displayed.
This is determined each time a write is made to the 'databuffer', prevent subsequent uop of the same instruction from writing to the 'dataBuffer'.

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VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector i

VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector instructions other than 'unit-stride' can only be issued on the first port.
Scalars and 'unit-stride' instruction can be emitted at either port if the 'Lsq' allows allocation.

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StoreQueue: sq entries with exception can deq without allvalid (#3090)

However, databuffer.io.enq.bits.vecValid will be false so this store
will not actually write into sbuffer.

StoreQueue: fix forward logic

StoreQueue: fix st mmio uop selection

LoadQueueRAW: use grouped instead of sliding

LoadQueueRAW: simplify group logic

LoadQueueReplay: fix enq ready logic