1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 129 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 130 131 uftb.io.in.bits.resp_in(0) := resp_in 132 tage.io.in.bits.resp_in(0) := uftb.io.out 133 ftb.io.in.bits.resp_in(0) := tage.io.out 134 ittage.io.in.bits.resp_in(0) := ftb.io.out 135 ras.io.in.bits.resp_in(0) := ittage.io.out 136 137 (preds, ras.io.out) 138 }, 139 ICacheECCForceError: Boolean = false, 140 IBufSize: Int = 48, 141 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 8, 145 RobCommitWidth: Int = 8, 146 RabCommitWidth: Int = 6, 147 MaxUopSize: Int = 65, 148 EnableRenameSnapshot: Boolean = true, 149 RenameSnapshotNum: Int = 4, 150 FtqSize: Int = 64, 151 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 152 IntLogicRegs: Int = 32, 153 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 154 VecLogicRegs: Int = 32 + 15, // 15: tmp 155 V0LogicRegs: Int = 1, // V0 156 VlLogicRegs: Int = 1, // Vl 157 V0_IDX: Int = 0, 158 Vl_IDX: Int = 0, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 IssueQueueCompEntrySize: Int = 16, 176 dpParams: DispatchParameters = DispatchParameters( 177 IntDqSize = 16, 178 FpDqSize = 16, 179 LsDqSize = 18, 180 IntDqDeqWidth = 8, 181 FpDqDeqWidth = 6, 182 VecDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 fpPreg: PregParams = FpPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 vfPreg: VfPregParams = VfPregParams( 196 numEntries = 128, 197 numRead = None, 198 numWrite = None, 199 ), 200 v0Preg: V0PregParams = V0PregParams( 201 numEntries = 22, 202 numRead = None, 203 numWrite = None, 204 ), 205 vlPreg: VlPregParams = VlPregParams( 206 numEntries = 32, 207 numRead = None, 208 numWrite = None, 209 ), 210 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 211 LoadPipelineWidth: Int = 3, 212 StorePipelineWidth: Int = 2, 213 VecLoadPipelineWidth: Int = 2, 214 VecStorePipelineWidth: Int = 2, 215 VecMemSrcInWidth: Int = 2, 216 VecMemInstWbWidth: Int = 1, 217 VecMemDispatchWidth: Int = 1, 218 VecMemDispatchMaxNumber: Int = 16, 219 VecMemUnitStrideMaxFlowNum: Int = 2, 220 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 221 StoreBufferSize: Int = 16, 222 StoreBufferThreshold: Int = 7, 223 EnsbufferWidth: Int = 2, 224 LoadDependencyWidth: Int = 2, 225 // ============ VLSU ============ 226 VlMergeBufferSize: Int = 16, 227 VsMergeBufferSize: Int = 16, 228 UopWritebackWidth: Int = 2, 229 VLUopWritebackWidth: Int = 2, 230 VSUopWritebackWidth: Int = 1, 231 VSegmentBufferSize: Int = 8, 232 // ============================== 233 UncacheBufferSize: Int = 4, 234 EnableLoadToLoadForward: Boolean = false, 235 EnableFastForward: Boolean = true, 236 EnableLdVioCheckAfterReset: Boolean = true, 237 EnableSoftPrefetchAfterReset: Boolean = true, 238 EnableCacheErrorAfterReset: Boolean = true, 239 EnableAccurateLoadError: Boolean = false, 240 EnableUncacheWriteOutstanding: Boolean = false, 241 EnableStorePrefetchAtIssue: Boolean = false, 242 EnableStorePrefetchAtCommit: Boolean = false, 243 EnableAtCommitMissTrigger: Boolean = true, 244 EnableStorePrefetchSMS: Boolean = false, 245 EnableStorePrefetchSPB: Boolean = false, 246 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 247 MMUVmidLen: Int = 14, 248 ReSelectLen: Int = 7, // load replay queue replay select counter len 249 iwpuParameters: WPUParameters = WPUParameters( 250 enWPU = false, 251 algoName = "mmru", 252 isICache = true, 253 ), 254 dwpuParameters: WPUParameters = WPUParameters( 255 enWPU = false, 256 algoName = "mmru", 257 enCfPred = false, 258 isICache = false, 259 ), 260 itlbParameters: TLBParameters = TLBParameters( 261 name = "itlb", 262 fetchi = true, 263 useDmode = false, 264 NWays = 48, 265 ), 266 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 267 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 268 ldtlbParameters: TLBParameters = TLBParameters( 269 name = "ldtlb", 270 NWays = 48, 271 outReplace = false, 272 partialStaticPMP = true, 273 outsideRecvFlush = true, 274 saveLevel = true, 275 lgMaxSize = 4 276 ), 277 sttlbParameters: TLBParameters = TLBParameters( 278 name = "sttlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = true, 284 lgMaxSize = 4 285 ), 286 hytlbParameters: TLBParameters = TLBParameters( 287 name = "hytlb", 288 NWays = 48, 289 outReplace = false, 290 partialStaticPMP = true, 291 outsideRecvFlush = true, 292 saveLevel = true, 293 lgMaxSize = 4 294 ), 295 pftlbParameters: TLBParameters = TLBParameters( 296 name = "pftlb", 297 NWays = 48, 298 outReplace = false, 299 partialStaticPMP = true, 300 outsideRecvFlush = true, 301 saveLevel = true, 302 lgMaxSize = 4 303 ), 304 l2ToL1tlbParameters: TLBParameters = TLBParameters( 305 name = "l2tlb", 306 NWays = 48, 307 outReplace = false, 308 partialStaticPMP = true, 309 outsideRecvFlush = true, 310 saveLevel = true 311 ), 312 refillBothTlb: Boolean = false, 313 btlbParameters: TLBParameters = TLBParameters( 314 name = "btlb", 315 NWays = 48, 316 ), 317 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 318 NumPerfCounters: Int = 16, 319 icacheParameters: ICacheParameters = ICacheParameters( 320 tagECC = Some("parity"), 321 dataECC = Some("parity"), 322 replacer = Some("setplru"), 323 nMissEntries = 2, 324 nProbeEntries = 2, 325 nPrefetchEntries = 12, 326 nPrefBufferEntries = 32, 327 ), 328 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 329 tagECC = Some("secded"), 330 dataECC = Some("secded"), 331 replacer = Some("setplru"), 332 nMissEntries = 16, 333 nProbeEntries = 8, 334 nReleaseEntries = 18, 335 nMaxPrefetchEntry = 6, 336 )), 337 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 338 name = "l2", 339 ways = 8, 340 sets = 1024, // default 512KB L2 341 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 342 coupledL2.prefetch.TPParameters()), 343 )), 344 L2NBanks: Int = 1, 345 usePTWRepeater: Boolean = false, 346 softTLB: Boolean = false, // dpi-c l1tlb debug only 347 softPTW: Boolean = false, // dpi-c l2tlb debug only 348 softPTWDelay: Int = 1 349){ 350 def vlWidth = log2Up(VLEN) + 1 351 352 /** 353 * the minimum element length of vector elements 354 */ 355 val minVecElen: Int = 8 356 357 /** 358 * the maximum number of elements in vector register 359 */ 360 val maxElemPerVreg: Int = VLEN / minVecElen 361 362 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 363 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 364 365 val intSchdParams = { 366 implicit val schdType: SchedulerType = IntScheduler() 367 SchdBlockParams(Seq( 368 IssueBlockParams(Seq( 369 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 370 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 371 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 372 IssueBlockParams(Seq( 373 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 374 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 375 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 376 IssueBlockParams(Seq( 377 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 378 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 379 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 380 IssueBlockParams(Seq( 381 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 382 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 383 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 384 ), 385 numPregs = intPreg.numEntries, 386 numDeqOutside = 0, 387 schdType = schdType, 388 rfDataWidth = intPreg.dataCfg.dataWidth, 389 numUopIn = dpParams.IntDqDeqWidth, 390 ) 391 } 392 393 val fpSchdParams = { 394 implicit val schdType: SchedulerType = FpScheduler() 395 SchdBlockParams(Seq( 396 IssueBlockParams(Seq( 397 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 398 ), numEntries = 18, numEnq = 2, numComp = 16), 399 IssueBlockParams(Seq( 400 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 401 ), numEntries = 18, numEnq = 2, numComp = 16), 402 IssueBlockParams(Seq( 403 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 404 ), numEntries = 18, numEnq = 2, numComp = 16), 405 IssueBlockParams(Seq( 406 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 407 ), numEntries = 18, numEnq = 2, numComp = 16), 408 IssueBlockParams(Seq( 409 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 410 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 411 ), numEntries = 18, numEnq = 2, numComp = 16), 412 ), 413 numPregs = fpPreg.numEntries, 414 numDeqOutside = 0, 415 schdType = schdType, 416 rfDataWidth = fpPreg.dataCfg.dataWidth, 417 numUopIn = dpParams.VecDqDeqWidth, 418 ) 419 } 420 421 val vfSchdParams = { 422 implicit val schdType: SchedulerType = VfScheduler() 423 SchdBlockParams(Seq( 424 IssueBlockParams(Seq( 425 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 426 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 427 ), numEntries = 16, numEnq = 2, numComp = 14), 428 IssueBlockParams(Seq( 429 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 430 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 431 ), numEntries = 16, numEnq = 2, numComp = 14), 432 IssueBlockParams(Seq( 433 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 434 ), numEntries = 10, numEnq = 2, numComp = 8), 435 ), 436 numPregs = vfPreg.numEntries, 437 numDeqOutside = 0, 438 schdType = schdType, 439 rfDataWidth = vfPreg.dataCfg.dataWidth, 440 numUopIn = dpParams.VecDqDeqWidth, 441 ) 442 } 443 444 val memSchdParams = { 445 implicit val schdType: SchedulerType = MemScheduler() 446 val rfDataWidth = 64 447 448 SchdBlockParams(Seq( 449 IssueBlockParams(Seq( 450 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 451 ), numEntries = 16, numEnq = 2, numComp = 14), 452 IssueBlockParams(Seq( 453 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 454 ), numEntries = 16, numEnq = 2, numComp = 14), 455 IssueBlockParams(Seq( 456 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 457 ), numEntries = 16, numEnq = 2, numComp = 14), 458 IssueBlockParams(Seq( 459 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 463 ), numEntries = 16, numEnq = 2, numComp = 14), 464 IssueBlockParams(Seq( 465 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 466 ), numEntries = 16, numEnq = 2, numComp = 14), 467 IssueBlockParams(Seq( 468 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 469 ), numEntries = 16, numEnq = 2, numComp = 14), 470 IssueBlockParams(Seq( 471 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 472 ), numEntries = 16, numEnq = 2, numComp = 14), 473 IssueBlockParams(Seq( 474 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 475 ), numEntries = 16, numEnq = 2, numComp = 14), 476 ), 477 numPregs = intPreg.numEntries max vfPreg.numEntries, 478 numDeqOutside = 0, 479 schdType = schdType, 480 rfDataWidth = rfDataWidth, 481 numUopIn = dpParams.LsDqDeqWidth, 482 ) 483 } 484 485 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 486 487 def iqWakeUpParams = { 488 Seq( 489 WakeUpConfig( 490 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 491 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 492 ), 493 WakeUpConfig( 494 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 495 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 496 ), 497 WakeUpConfig( 498 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 499 Seq("STD0", "STD1") 500 ), 501 WakeUpConfig( 502 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 503 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 504 ), 505 ).flatten 506 } 507 508 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 509 510 val backendParams: BackendParams = backend.BackendParams( 511 Map( 512 IntScheduler() -> intSchdParams, 513 FpScheduler() -> fpSchdParams, 514 VfScheduler() -> vfSchdParams, 515 MemScheduler() -> memSchdParams, 516 ), 517 Seq( 518 intPreg, 519 fpPreg, 520 vfPreg, 521 v0Preg, 522 vlPreg, 523 fakeIntPreg 524 ), 525 iqWakeUpParams, 526 ) 527} 528 529case object DebugOptionsKey extends Field[DebugOptions] 530 531case class DebugOptions 532( 533 FPGAPlatform: Boolean = false, 534 ResetGen: Boolean = false, 535 EnableDifftest: Boolean = false, 536 AlwaysBasicDiff: Boolean = true, 537 EnableDebug: Boolean = false, 538 EnablePerfDebug: Boolean = true, 539 UseDRAMSim: Boolean = false, 540 EnableConstantin: Boolean = false, 541 EnableChiselDB: Boolean = false, 542 AlwaysBasicDB: Boolean = true, 543 EnableTopDown: Boolean = false, 544 EnableRollingDB: Boolean = false 545) 546 547trait HasXSParameter { 548 549 implicit val p: Parameters 550 551 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 552 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 553 554 def coreParams = p(XSCoreParamsKey) 555 def env = p(DebugOptionsKey) 556 557 def XLEN = coreParams.XLEN 558 def VLEN = coreParams.VLEN 559 def ELEN = coreParams.ELEN 560 def HSXLEN = coreParams.HSXLEN 561 val minFLen = 32 562 val fLen = 64 563 def hartIdLen = p(MaxHartIdBits) 564 val xLen = XLEN 565 566 def HasMExtension = coreParams.HasMExtension 567 def HasCExtension = coreParams.HasCExtension 568 def HasHExtension = coreParams.HasHExtension 569 def HasDiv = coreParams.HasDiv 570 def HasIcache = coreParams.HasICache 571 def HasDcache = coreParams.HasDCache 572 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 573 def GPAddrBits = coreParams.GPAddrBits 574 def VAddrBits = { 575 if(HasHExtension){ 576 coreParams.GPAddrBits 577 }else{ 578 coreParams.VAddrBits 579 } 580 } // VAddrBits is Virtual Memory addr bits 581 582 def AsidLength = coreParams.AsidLength 583 def VmidLength = coreParams.VmidLength 584 def ReSelectLen = coreParams.ReSelectLen 585 def AddrBytes = AddrBits / 8 // unused 586 def DataBits = XLEN 587 def DataBytes = DataBits / 8 588 def VDataBytes = VLEN / 8 589 def HasFPU = coreParams.HasFPU 590 def HasVPU = coreParams.HasVPU 591 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 592 def FetchWidth = coreParams.FetchWidth 593 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 594 def EnableBPU = coreParams.EnableBPU 595 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 596 def EnableRAS = coreParams.EnableRAS 597 def EnableLB = coreParams.EnableLB 598 def EnableLoop = coreParams.EnableLoop 599 def EnableSC = coreParams.EnableSC 600 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 601 def HistoryLength = coreParams.HistoryLength 602 def EnableGHistDiff = coreParams.EnableGHistDiff 603 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 604 def EnableClockGate = coreParams.EnableClockGate 605 def UbtbGHRLength = coreParams.UbtbGHRLength 606 def UbtbSize = coreParams.UbtbSize 607 def EnableFauFTB = coreParams.EnableFauFTB 608 def FtbSize = coreParams.FtbSize 609 def FtbWays = coreParams.FtbWays 610 def RasSize = coreParams.RasSize 611 def RasSpecSize = coreParams.RasSpecSize 612 def RasCtrSize = coreParams.RasCtrSize 613 614 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 615 coreParams.branchPredictor(resp_in, p) 616 } 617 def numBr = coreParams.numBr 618 def TageTableInfos = coreParams.TageTableInfos 619 def TageBanks = coreParams.numBr 620 def SCNRows = coreParams.SCNRows 621 def SCCtrBits = coreParams.SCCtrBits 622 def SCHistLens = coreParams.SCHistLens 623 def SCNTables = coreParams.SCNTables 624 625 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 626 case ((n, cb), h) => (n, cb, h) 627 } 628 def ITTageTableInfos = coreParams.ITTageTableInfos 629 type FoldedHistoryInfo = Tuple2[Int, Int] 630 def foldedGHistInfos = 631 (TageTableInfos.map{ case (nRows, h, t) => 632 if (h > 0) 633 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 634 else 635 Set[FoldedHistoryInfo]() 636 }.reduce(_++_).toSet ++ 637 SCTableInfos.map{ case (nRows, _, h) => 638 if (h > 0) 639 Set((h, min(log2Ceil(nRows/TageBanks), h))) 640 else 641 Set[FoldedHistoryInfo]() 642 }.reduce(_++_).toSet ++ 643 ITTageTableInfos.map{ case (nRows, h, t) => 644 if (h > 0) 645 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 646 else 647 Set[FoldedHistoryInfo]() 648 }.reduce(_++_) ++ 649 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 650 ).toList 651 652 653 654 def CacheLineSize = coreParams.CacheLineSize 655 def CacheLineHalfWord = CacheLineSize / 16 656 def ExtHistoryLength = HistoryLength + 64 657 def ICacheECCForceError = coreParams.ICacheECCForceError 658 def IBufSize = coreParams.IBufSize 659 def IBufNBank = coreParams.IBufNBank 660 def backendParams: BackendParams = coreParams.backendParams 661 def DecodeWidth = coreParams.DecodeWidth 662 def RenameWidth = coreParams.RenameWidth 663 def CommitWidth = coreParams.CommitWidth 664 def RobCommitWidth = coreParams.RobCommitWidth 665 def RabCommitWidth = coreParams.RabCommitWidth 666 def MaxUopSize = coreParams.MaxUopSize 667 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 668 def RenameSnapshotNum = coreParams.RenameSnapshotNum 669 def FtqSize = coreParams.FtqSize 670 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 671 def IntLogicRegs = coreParams.IntLogicRegs 672 def FpLogicRegs = coreParams.FpLogicRegs 673 def VecLogicRegs = coreParams.VecLogicRegs 674 def V0LogicRegs = coreParams.V0LogicRegs 675 def VlLogicRegs = coreParams.VlLogicRegs 676 def V0_IDX = coreParams.V0_IDX 677 def Vl_IDX = coreParams.Vl_IDX 678 def IntPhyRegs = coreParams.intPreg.numEntries 679 def FpPhyRegs = coreParams.fpPreg.numEntries 680 def VfPhyRegs = coreParams.vfPreg.numEntries 681 def V0PhyRegs = coreParams.v0Preg.numEntries 682 def VlPhyRegs = coreParams.vlPreg.numEntries 683 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 684 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 685 def RobSize = coreParams.RobSize 686 def RabSize = coreParams.RabSize 687 def VTypeBufferSize = coreParams.VTypeBufferSize 688 /** 689 * the minimum element length of vector elements 690 */ 691 def minVecElen: Int = coreParams.minVecElen 692 693 /** 694 * the maximum number of elements in vector register 695 */ 696 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 697 698 def IntRefCounterWidth = log2Ceil(RobSize) 699 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 700 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 701 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 702 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 703 def LoadQueueRARSize = coreParams.LoadQueueRARSize 704 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 705 def RollbackGroupSize = coreParams.RollbackGroupSize 706 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 707 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 708 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 709 def StoreQueueSize = coreParams.StoreQueueSize 710 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 711 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 712 def VlsQueueSize = coreParams.VlsQueueSize 713 def dpParams = coreParams.dpParams 714 715 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 716 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 717 718 def NumRedirect = backendParams.numRedirect 719 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 720 def FtqRedirectAheadNum = NumRedirect 721 def LoadPipelineWidth = coreParams.LoadPipelineWidth 722 def StorePipelineWidth = coreParams.StorePipelineWidth 723 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 724 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 725 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 726 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 727 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 728 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 729 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 730 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 731 def StoreBufferSize = coreParams.StoreBufferSize 732 def StoreBufferThreshold = coreParams.StoreBufferThreshold 733 def EnsbufferWidth = coreParams.EnsbufferWidth 734 def LoadDependencyWidth = coreParams.LoadDependencyWidth 735 def VlMergeBufferSize = coreParams.VlMergeBufferSize 736 def VsMergeBufferSize = coreParams.VsMergeBufferSize 737 def UopWritebackWidth = coreParams.UopWritebackWidth 738 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 739 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 740 def VSegmentBufferSize = coreParams.VSegmentBufferSize 741 def UncacheBufferSize = coreParams.UncacheBufferSize 742 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 743 def EnableFastForward = coreParams.EnableFastForward 744 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 745 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 746 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 747 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 748 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 749 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 750 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 751 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 752 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 753 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 754 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 755 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 756 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 757 def asidLen = coreParams.MMUAsidLen 758 def vmidLen = coreParams.MMUVmidLen 759 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 760 def refillBothTlb = coreParams.refillBothTlb 761 def iwpuParam = coreParams.iwpuParameters 762 def dwpuParam = coreParams.dwpuParameters 763 def itlbParams = coreParams.itlbParameters 764 def ldtlbParams = coreParams.ldtlbParameters 765 def sttlbParams = coreParams.sttlbParameters 766 def hytlbParams = coreParams.hytlbParameters 767 def pftlbParams = coreParams.pftlbParameters 768 def l2ToL1Params = coreParams.l2ToL1tlbParameters 769 def btlbParams = coreParams.btlbParameters 770 def l2tlbParams = coreParams.l2tlbParameters 771 def NumPerfCounters = coreParams.NumPerfCounters 772 773 def instBytes = if (HasCExtension) 2 else 4 774 def instOffsetBits = log2Ceil(instBytes) 775 776 def icacheParameters = coreParams.icacheParameters 777 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 778 779 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 780 // for constrained LR/SC loop 781 def LRSCCycles = 64 782 // for lr storm 783 def LRSCBackOff = 8 784 785 // cache hierarchy configurations 786 def l1BusDataWidth = 256 787 788 // load violation predict 789 def ResetTimeMax2Pow = 20 //1078576 790 def ResetTimeMin2Pow = 10 //1024 791 // wait table parameters 792 def WaitTableSize = 1024 793 def MemPredPCWidth = log2Up(WaitTableSize) 794 def LWTUse2BitCounter = true 795 // store set parameters 796 def SSITSize = WaitTableSize 797 def LFSTSize = 32 798 def SSIDWidth = log2Up(LFSTSize) 799 def LFSTWidth = 4 800 def StoreSetEnable = true // LWT will be disabled if SS is enabled 801 def LFSTEnable = true 802 803 def PCntIncrStep: Int = 6 804 def numPCntHc: Int = 25 805 def numPCntPtw: Int = 19 806 807 def numCSRPCntFrontend = 8 808 def numCSRPCntCtrl = 8 809 def numCSRPCntLsu = 8 810 def numCSRPCntHc = 5 811 def printEventCoding = true 812 813 // Parameters for Sdtrig extension 814 protected def TriggerNum = 4 815 protected def TriggerChainMaxLength = 2 816} 817