1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend._ 26import xiangshan.backend.fu.fpu._ 27import xiangshan.backend.rob.RobLsqIO 28import xiangshan.cache._ 29import xiangshan.cache.mmu._ 30import xiangshan.frontend.FtqPtr 31import xiangshan.ExceptionNO._ 32import xiangshan.mem.mdp._ 33import xiangshan.backend.Bundles.{DynInst, MemExuOutput, MemMicroOpRbExt} 34import xiangshan.backend.rob.RobPtr 35 36class LqPtr(implicit p: Parameters) extends CircularQueuePtr[LqPtr]( 37 p => p(XSCoreParamsKey).VirtualLoadQueueSize 38){ 39} 40 41object LqPtr { 42 def apply(f: Bool, v: UInt)(implicit p: Parameters): LqPtr = { 43 val ptr = Wire(new LqPtr) 44 ptr.flag := f 45 ptr.value := v 46 ptr 47 } 48} 49 50trait HasLoadHelper { this: XSModule => 51 def rdataHelper(uop: DynInst, rdata: UInt): UInt = { 52 val fpWen = uop.fpWen 53 LookupTree(uop.fuOpType, List( 54 LSUOpType.lb -> SignExt(rdata(7, 0) , XLEN), 55 LSUOpType.lh -> SignExt(rdata(15, 0), XLEN), 56 /* 57 riscv-spec-20191213: 12.2 NaN Boxing of Narrower Values 58 Any operation that writes a narrower result to an f register must write 59 all 1s to the uppermost FLEN−n bits to yield a legal NaN-boxed value. 60 */ 61 LSUOpType.lw -> Mux(fpWen, FPU.box(rdata, FPU.S), SignExt(rdata(31, 0), XLEN)), 62 LSUOpType.ld -> Mux(fpWen, FPU.box(rdata, FPU.D), SignExt(rdata(63, 0), XLEN)), 63 LSUOpType.lbu -> ZeroExt(rdata(7, 0) , XLEN), 64 LSUOpType.lhu -> ZeroExt(rdata(15, 0), XLEN), 65 LSUOpType.lwu -> ZeroExt(rdata(31, 0), XLEN), 66 67 // hypervisor 68 LSUOpType.hlvb -> SignExt(rdata(7, 0), XLEN), 69 LSUOpType.hlvh -> SignExt(rdata(15, 0), XLEN), 70 LSUOpType.hlvw -> SignExt(rdata(31, 0), XLEN), 71 LSUOpType.hlvd -> SignExt(rdata(63, 0), XLEN), 72 LSUOpType.hlvbu -> ZeroExt(rdata(7, 0), XLEN), 73 LSUOpType.hlvhu -> ZeroExt(rdata(15, 0), XLEN), 74 LSUOpType.hlvwu -> ZeroExt(rdata(31, 0), XLEN), 75 LSUOpType.hlvxhu -> ZeroExt(rdata(15, 0), XLEN), 76 LSUOpType.hlvxwu -> ZeroExt(rdata(31, 0), XLEN), 77 )) 78 } 79 80 def genRdataOH(uop: DynInst): UInt = { 81 val fuOpType = uop.fuOpType 82 val fpWen = uop.fpWen 83 val result = Cat( 84 (fuOpType === LSUOpType.lw && fpWen), 85 (fuOpType === LSUOpType.lw && !fpWen) || (fuOpType === LSUOpType.hlvw), 86 (fuOpType === LSUOpType.lh) || (fuOpType === LSUOpType.hlvh), 87 (fuOpType === LSUOpType.lb) || (fuOpType === LSUOpType.hlvb), 88 (fuOpType === LSUOpType.ld) || (fuOpType === LSUOpType.hlvd), 89 (fuOpType === LSUOpType.lwu) || (fuOpType === LSUOpType.hlvwu) || (fuOpType === LSUOpType.hlvxwu), 90 (fuOpType === LSUOpType.lhu) || (fuOpType === LSUOpType.hlvhu) || (fuOpType === LSUOpType.hlvxhu), 91 (fuOpType === LSUOpType.lbu) || (fuOpType === LSUOpType.hlvbu), 92 ) 93 result 94 } 95 96 def newRdataHelper(select: UInt, rdata: UInt): UInt = { 97 XSError(PopCount(select) > 1.U, "data selector must be One-Hot!\n") 98 val selData = Seq( 99 ZeroExt(rdata(7, 0), XLEN), 100 ZeroExt(rdata(15, 0), XLEN), 101 ZeroExt(rdata(31, 0), XLEN), 102 rdata(63, 0), 103 SignExt(rdata(7, 0) , XLEN), 104 SignExt(rdata(15, 0) , XLEN), 105 SignExt(rdata(31, 0) , XLEN), 106 FPU.box(rdata, FPU.S) 107 ) 108 Mux1H(select, selData) 109 } 110 111 def genDataSelectByOffset(addrOffset: UInt): Vec[Bool] = { 112 require(addrOffset.getWidth == 4) 113 VecInit((0 until 16).map{ case i => 114 addrOffset === i.U 115 }) 116 } 117 118 def rdataVecHelper(alignedType: UInt, rdata: UInt): UInt = { 119 LookupTree(alignedType, List( 120 "b00".U -> ZeroExt(rdata(7, 0), VLEN), 121 "b01".U -> ZeroExt(rdata(15, 0), VLEN), 122 "b10".U -> ZeroExt(rdata(31, 0), VLEN), 123 "b11".U -> ZeroExt(rdata(63, 0), VLEN) 124 )) 125 } 126} 127 128class LqEnqIO(implicit p: Parameters) extends MemBlockBundle { 129 val canAccept = Output(Bool()) 130 val sqCanAccept = Input(Bool()) 131 val needAlloc = Vec(LSQEnqWidth, Input(Bool())) 132 val req = Vec(LSQEnqWidth, Flipped(ValidIO(new DynInst))) 133 val resp = Vec(LSQEnqWidth, Output(new LqPtr)) 134} 135 136class LqTriggerIO(implicit p: Parameters) extends XSBundle { 137 val hitLoadAddrTriggerHitVec = Input(Vec(TriggerNum, Bool())) 138 val lqLoadAddrTriggerHitVec = Output(Vec(TriggerNum, Bool())) 139} 140 141class LoadQueueTopDownIO(implicit p: Parameters) extends XSBundle { 142 val robHeadVaddr = Flipped(Valid(UInt(VAddrBits.W))) 143 val robHeadTlbReplay = Output(Bool()) 144 val robHeadTlbMiss = Output(Bool()) 145 val robHeadLoadVio = Output(Bool()) 146 val robHeadLoadMSHR = Output(Bool()) 147 val robHeadMissInDTlb = Input(Bool()) 148 val robHeadOtherReplay = Output(Bool()) 149} 150 151class LoadQueue(implicit p: Parameters) extends XSModule 152 with HasDCacheParameters 153 with HasCircularQueuePtrHelper 154 with HasLoadHelper 155 with HasPerfEvents 156{ 157 val io = IO(new Bundle() { 158 val redirect = Flipped(Valid(new Redirect)) 159 val vecFeedback = Vec(VecLoadPipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 160 val enq = new LqEnqIO 161 val ldu = new Bundle() { 162 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 163 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 164 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 165 } 166 val sta = new Bundle() { 167 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 168 } 169 val std = new Bundle() { 170 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput(isVector = true)))) // from store_s0, store data, send to sq from rs 171 } 172 val sq = new Bundle() { 173 val stAddrReadySqPtr = Input(new SqPtr) 174 val stAddrReadyVec = Input(Vec(StoreQueueSize, Bool())) 175 val stDataReadySqPtr = Input(new SqPtr) 176 val stDataReadyVec = Input(Vec(StoreQueueSize, Bool())) 177 val stIssuePtr = Input(new SqPtr) 178 val sqEmpty = Input(Bool()) 179 } 180 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 181 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 182 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 183 // val refill = Flipped(ValidIO(new Refill)) 184 val tl_d_channel = Input(new DcacheToLduForwardIO) 185 val release = Flipped(Valid(new Release)) 186 val nuke_rollback = Vec(StorePipelineWidth, Output(Valid(new Redirect))) 187 val nack_rollback = Output(Valid(new Redirect)) 188 val rob = Flipped(new RobLsqIO) 189 val uncache = new UncacheWordIO 190 val exceptionAddr = new ExceptionAddrIO 191 val lqFull = Output(Bool()) 192 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 193 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 194 val lq_rep_full = Output(Bool()) 195 val tlbReplayDelayCycleCtrl = Vec(4, Input(UInt(ReSelectLen.W))) 196 val l2_hint = Input(Valid(new L2ToL1Hint())) 197 val tlb_hint = Flipped(new TlbHintIO) 198 val lqEmpty = Output(Bool()) 199 200 val lqDeqPtr = Output(new LqPtr) 201 202 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 203 204 val debugTopDown = new LoadQueueTopDownIO 205 }) 206 207 val loadQueueRAR = Module(new LoadQueueRAR) // read-after-read violation 208 val loadQueueRAW = Module(new LoadQueueRAW) // read-after-write violation 209 val loadQueueReplay = Module(new LoadQueueReplay) // enqueue if need replay 210 val virtualLoadQueue = Module(new VirtualLoadQueue) // control state 211 val exceptionBuffer = Module(new LqExceptionBuffer) // exception buffer 212 val uncacheBuffer = Module(new UncacheBuffer) // uncache buffer 213 /** 214 * LoadQueueRAR 215 */ 216 loadQueueRAR.io.redirect <> io.redirect 217 loadQueueRAR.io.vecFeedback <> io.vecFeedback 218 loadQueueRAR.io.release <> io.release 219 loadQueueRAR.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 220 for (w <- 0 until LoadPipelineWidth) { 221 loadQueueRAR.io.query(w).req <> io.ldu.ldld_nuke_query(w).req // from load_s1 222 loadQueueRAR.io.query(w).resp <> io.ldu.ldld_nuke_query(w).resp // to load_s2 223 loadQueueRAR.io.query(w).revoke := io.ldu.ldld_nuke_query(w).revoke // from load_s3 224 } 225 226 /** 227 * LoadQueueRAW 228 */ 229 loadQueueRAW.io.redirect <> io.redirect 230 loadQueueRAW.io.vecFeedback <> io.vecFeedback 231 loadQueueRAW.io.storeIn <> io.sta.storeAddrIn 232 loadQueueRAW.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 233 loadQueueRAW.io.stIssuePtr <> io.sq.stIssuePtr 234 for (w <- 0 until LoadPipelineWidth) { 235 loadQueueRAW.io.query(w).req <> io.ldu.stld_nuke_query(w).req // from load_s1 236 loadQueueRAW.io.query(w).resp <> io.ldu.stld_nuke_query(w).resp // to load_s2 237 loadQueueRAW.io.query(w).revoke := io.ldu.stld_nuke_query(w).revoke // from load_s3 238 } 239 240 /** 241 * VirtualLoadQueue 242 */ 243 virtualLoadQueue.io.redirect <> io.redirect 244 virtualLoadQueue.io.vecCommit <> io.vecFeedback 245 virtualLoadQueue.io.enq <> io.enq 246 virtualLoadQueue.io.ldin <> io.ldu.ldin // from load_s3 247 virtualLoadQueue.io.lqFull <> io.lqFull 248 virtualLoadQueue.io.lqDeq <> io.lqDeq 249 virtualLoadQueue.io.lqCancelCnt <> io.lqCancelCnt 250 virtualLoadQueue.io.lqEmpty <> io.lqEmpty 251 virtualLoadQueue.io.ldWbPtr <> io.lqDeqPtr 252 253 /** 254 * Load queue exception buffer 255 */ 256 exceptionBuffer.io.redirect <> io.redirect 257 for (i <- 0 until LoadPipelineWidth) { 258 exceptionBuffer.io.req(i).valid := io.ldu.ldin(i).valid && !io.ldu.ldin(i).bits.isvec // from load_s3 259 exceptionBuffer.io.req(i).bits := io.ldu.ldin(i).bits 260 } 261 // vlsu exception! 262 for (i <- 0 until VecLoadPipelineWidth) { 263 exceptionBuffer.io.req(LoadPipelineWidth + i).valid := io.vecFeedback(i).valid && io.vecFeedback(i).bits.feedback(VecFeedbacks.FLUSH) // have exception 264 exceptionBuffer.io.req(LoadPipelineWidth + i).bits := DontCare 265 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.vaddr := io.vecFeedback(i).bits.vaddr 266 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.uopIdx := io.vecFeedback(i).bits.uopidx 267 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.robIdx := io.vecFeedback(i).bits.robidx 268 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.vpu.vstart := io.vecFeedback(i).bits.vstart 269 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.vpu.vl := io.vecFeedback(i).bits.vl 270 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.exceptionVec := io.vecFeedback(i).bits.exceptionVec 271 } 272 // mmio non-data error exception 273 exceptionBuffer.io.req.last := uncacheBuffer.io.exception 274 275 io.exceptionAddr <> exceptionBuffer.io.exceptionAddr 276 277 /** 278 * Load uncache buffer 279 */ 280 uncacheBuffer.io.redirect <> io.redirect 281 uncacheBuffer.io.ldout <> io.ldout 282 uncacheBuffer.io.ld_raw_data <> io.ld_raw_data 283 uncacheBuffer.io.rob <> io.rob 284 uncacheBuffer.io.uncache <> io.uncache 285 uncacheBuffer.io.trigger <> io.trigger 286 for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) { 287 buff.valid := io.ldu.ldin(w).valid // from load_s3 288 buff.bits := io.ldu.ldin(w).bits // from load_s3 289 } 290 291 292 io.nuke_rollback := loadQueueRAW.io.rollback 293 io.nack_rollback := uncacheBuffer.io.rollback 294 295 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 296 297 /** 298 * LoadQueueReplay 299 */ 300 loadQueueReplay.io.redirect <> io.redirect 301 loadQueueReplay.io.enq <> io.ldu.ldin // from load_s3 302 loadQueueReplay.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 303 loadQueueReplay.io.storeDataIn <> io.std.storeDataIn // from store_s0 304 loadQueueReplay.io.replay <> io.replay 305 //loadQueueReplay.io.refill <> io.refill 306 loadQueueReplay.io.tl_d_channel <> io.tl_d_channel 307 loadQueueReplay.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 308 loadQueueReplay.io.stAddrReadyVec <> io.sq.stAddrReadyVec 309 loadQueueReplay.io.stDataReadySqPtr <> io.sq.stDataReadySqPtr 310 loadQueueReplay.io.stDataReadyVec <> io.sq.stDataReadyVec 311 loadQueueReplay.io.sqEmpty <> io.sq.sqEmpty 312 loadQueueReplay.io.lqFull <> io.lq_rep_full 313 loadQueueReplay.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 314 loadQueueReplay.io.rarFull <> loadQueueRAR.io.lqFull 315 loadQueueReplay.io.rawFull <> loadQueueRAW.io.lqFull 316 loadQueueReplay.io.l2_hint <> io.l2_hint 317 loadQueueReplay.io.tlb_hint <> io.tlb_hint 318 loadQueueReplay.io.tlbReplayDelayCycleCtrl <> io.tlbReplayDelayCycleCtrl 319 // TODO: implement it! 320 loadQueueReplay.io.vecFeedback := io.vecFeedback 321 322 loadQueueReplay.io.debugTopDown <> io.debugTopDown 323 324 val full_mask = Cat(loadQueueRAR.io.lqFull, loadQueueRAW.io.lqFull, loadQueueReplay.io.lqFull) 325 XSPerfAccumulate("full_mask_000", full_mask === 0.U) 326 XSPerfAccumulate("full_mask_001", full_mask === 1.U) 327 XSPerfAccumulate("full_mask_010", full_mask === 2.U) 328 XSPerfAccumulate("full_mask_011", full_mask === 3.U) 329 XSPerfAccumulate("full_mask_100", full_mask === 4.U) 330 XSPerfAccumulate("full_mask_101", full_mask === 5.U) 331 XSPerfAccumulate("full_mask_110", full_mask === 6.U) 332 XSPerfAccumulate("full_mask_111", full_mask === 7.U) 333 XSPerfAccumulate("nuke_rollback", io.nuke_rollback.map(_.valid).reduce(_ || _).asUInt) 334 XSPerfAccumulate("nack_rollabck", io.nack_rollback.valid) 335 336 // perf cnt 337 val perfEvents = Seq(virtualLoadQueue, loadQueueRAR, loadQueueRAW, loadQueueReplay).flatMap(_.getPerfEvents) ++ 338 Seq( 339 ("full_mask_000", full_mask === 0.U), 340 ("full_mask_001", full_mask === 1.U), 341 ("full_mask_010", full_mask === 2.U), 342 ("full_mask_011", full_mask === 3.U), 343 ("full_mask_100", full_mask === 4.U), 344 ("full_mask_101", full_mask === 5.U), 345 ("full_mask_110", full_mask === 6.U), 346 ("full_mask_111", full_mask === 7.U), 347 ("nuke_rollback", io.nuke_rollback.map(_.valid).reduce(_ || _).asUInt), 348 ("nack_rollback", io.nack_rollback.valid) 349 ) 350 generatePerfEvent() 351 // end 352}