1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBitsSv39: Int = 39, 72 GPAddrBitsSv39x4: Int = 41, 73 VAddrBitsSv48: Int = 48, 74 GPAddrBitsSv48x4: Int = 50, 75 HasFPU: Boolean = true, 76 HasVPU: Boolean = true, 77 HasCustomCSRCacheOp: Boolean = true, 78 FetchWidth: Int = 8, 79 AsidLength: Int = 16, 80 VmidLength: Int = 14, 81 EnableBPU: Boolean = true, 82 EnableBPD: Boolean = true, 83 EnableRAS: Boolean = true, 84 EnableLB: Boolean = false, 85 EnableLoop: Boolean = true, 86 EnableSC: Boolean = true, 87 EnbaleTlbDebug: Boolean = false, 88 EnableClockGate: Boolean = true, 89 EnableJal: Boolean = false, 90 EnableFauFTB: Boolean = true, 91 EnableSv48: Boolean = true, 92 UbtbGHRLength: Int = 4, 93 // HistoryLength: Int = 512, 94 EnableGHistDiff: Boolean = true, 95 EnableCommitGHistDiff: Boolean = true, 96 UbtbSize: Int = 256, 97 FtbSize: Int = 2048, 98 RasSize: Int = 16, 99 RasSpecSize: Int = 32, 100 RasCtrSize: Int = 3, 101 CacheLineSize: Int = 512, 102 FtbWays: Int = 4, 103 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 104 // Sets Hist Tag 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 122 (resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val uftb = Module(new FauFTB()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(uftb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 132 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 133 134 uftb.io.in.bits.resp_in(0) := resp_in 135 tage.io.in.bits.resp_in(0) := uftb.io.out 136 ftb.io.in.bits.resp_in(0) := tage.io.out 137 ittage.io.in.bits.resp_in(0) := ftb.io.out 138 ras.io.in.bits.resp_in(0) := ittage.io.out 139 140 (preds, ras.io.out) 141 }, 142 ICacheForceMetaECCError: Boolean = false, 143 ICacheForceDataECCError: Boolean = false, 144 IBufSize: Int = 48, 145 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 146 DecodeWidth: Int = 6, 147 RenameWidth: Int = 6, 148 CommitWidth: Int = 8, 149 RobCommitWidth: Int = 8, 150 RabCommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 15, // 15: tmp 159 V0LogicRegs: Int = 1, // V0 160 VlLogicRegs: Int = 1, // Vl 161 V0_IDX: Int = 0, 162 Vl_IDX: Int = 0, 163 NRPhyRegs: Int = 192, 164 VirtualLoadQueueSize: Int = 72, 165 LoadQueueRARSize: Int = 72, 166 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 167 RollbackGroupSize: Int = 8, 168 LoadQueueReplaySize: Int = 72, 169 LoadUncacheBufferSize: Int = 20, 170 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 171 StoreQueueSize: Int = 64, 172 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 173 StoreQueueForwardWithMask: Boolean = true, 174 VlsQueueSize: Int = 8, 175 RobSize: Int = 160, 176 RabSize: Int = 256, 177 VTypeBufferSize: Int = 64, // used to reorder vtype 178 IssueQueueSize: Int = 24, 179 IssueQueueCompEntrySize: Int = 16, 180 dpParams: DispatchParameters = DispatchParameters( 181 IntDqSize = 16, 182 FpDqSize = 16, 183 LsDqSize = 18, 184 IntDqDeqWidth = 8, 185 FpDqDeqWidth = 6, 186 VecDqDeqWidth = 6, 187 LsDqDeqWidth = 6, 188 ), 189 intPreg: PregParams = IntPregParams( 190 numEntries = 224, 191 numRead = None, 192 numWrite = None, 193 ), 194 fpPreg: PregParams = FpPregParams( 195 numEntries = 192, 196 numRead = None, 197 numWrite = None, 198 ), 199 vfPreg: VfPregParams = VfPregParams( 200 numEntries = 128, 201 numRead = None, 202 numWrite = None, 203 ), 204 v0Preg: V0PregParams = V0PregParams( 205 numEntries = 22, 206 numRead = None, 207 numWrite = None, 208 ), 209 vlPreg: VlPregParams = VlPregParams( 210 numEntries = 32, 211 numRead = None, 212 numWrite = None, 213 ), 214 IntRegCacheSize: Int = 16, 215 MemRegCacheSize: Int = 12, 216 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 217 IfuRedirectNum: Int = 1, 218 LoadPipelineWidth: Int = 3, 219 StorePipelineWidth: Int = 2, 220 VecLoadPipelineWidth: Int = 2, 221 VecStorePipelineWidth: Int = 2, 222 VecMemSrcInWidth: Int = 2, 223 VecMemInstWbWidth: Int = 1, 224 VecMemDispatchWidth: Int = 1, 225 VecMemDispatchMaxNumber: Int = 16, 226 VecMemUnitStrideMaxFlowNum: Int = 2, 227 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 228 StoreBufferSize: Int = 16, 229 StoreBufferThreshold: Int = 7, 230 EnsbufferWidth: Int = 2, 231 LoadDependencyWidth: Int = 2, 232 // ============ VLSU ============ 233 VlMergeBufferSize: Int = 16, 234 VsMergeBufferSize: Int = 16, 235 UopWritebackWidth: Int = 2, 236 VLUopWritebackWidth: Int = 2, 237 VSUopWritebackWidth: Int = 1, 238 VSegmentBufferSize: Int = 8, 239 // ============================== 240 UncacheBufferSize: Int = 4, 241 EnableLoadToLoadForward: Boolean = false, 242 EnableFastForward: Boolean = true, 243 EnableLdVioCheckAfterReset: Boolean = true, 244 EnableSoftPrefetchAfterReset: Boolean = true, 245 EnableCacheErrorAfterReset: Boolean = true, 246 EnableAccurateLoadError: Boolean = false, 247 EnableUncacheWriteOutstanding: Boolean = false, 248 EnableHardwareStoreMisalign: Boolean = true, 249 EnableHardwareLoadMisalign: Boolean = true, 250 EnableStorePrefetchAtIssue: Boolean = false, 251 EnableStorePrefetchAtCommit: Boolean = false, 252 EnableAtCommitMissTrigger: Boolean = true, 253 EnableStorePrefetchSMS: Boolean = false, 254 EnableStorePrefetchSPB: Boolean = false, 255 HasRVA23CMO: Boolean = false, 256 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 257 MMUVmidLen: Int = 14, 258 ReSelectLen: Int = 7, // load replay queue replay select counter len 259 iwpuParameters: WPUParameters = WPUParameters( 260 enWPU = false, 261 algoName = "mmru", 262 isICache = true, 263 ), 264 dwpuParameters: WPUParameters = WPUParameters( 265 enWPU = false, 266 algoName = "mmru", 267 enCfPred = false, 268 isICache = false, 269 ), 270 itlbParameters: TLBParameters = TLBParameters( 271 name = "itlb", 272 fetchi = true, 273 useDmode = false, 274 NWays = 48, 275 ), 276 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 277 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 278 ldtlbParameters: TLBParameters = TLBParameters( 279 name = "ldtlb", 280 NWays = 48, 281 outReplace = false, 282 partialStaticPMP = true, 283 outsideRecvFlush = true, 284 saveLevel = false, 285 lgMaxSize = 4 286 ), 287 sttlbParameters: TLBParameters = TLBParameters( 288 name = "sttlb", 289 NWays = 48, 290 outReplace = false, 291 partialStaticPMP = true, 292 outsideRecvFlush = true, 293 saveLevel = false, 294 lgMaxSize = 4 295 ), 296 hytlbParameters: TLBParameters = TLBParameters( 297 name = "hytlb", 298 NWays = 48, 299 outReplace = false, 300 partialStaticPMP = true, 301 outsideRecvFlush = true, 302 saveLevel = false, 303 lgMaxSize = 4 304 ), 305 pftlbParameters: TLBParameters = TLBParameters( 306 name = "pftlb", 307 NWays = 48, 308 outReplace = false, 309 partialStaticPMP = true, 310 outsideRecvFlush = true, 311 saveLevel = false, 312 lgMaxSize = 4 313 ), 314 l2ToL1tlbParameters: TLBParameters = TLBParameters( 315 name = "l2tlb", 316 NWays = 48, 317 outReplace = false, 318 partialStaticPMP = true, 319 outsideRecvFlush = true, 320 saveLevel = false 321 ), 322 refillBothTlb: Boolean = false, 323 btlbParameters: TLBParameters = TLBParameters( 324 name = "btlb", 325 NWays = 48, 326 ), 327 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 328 NumPerfCounters: Int = 16, 329 icacheParameters: ICacheParameters = ICacheParameters( 330 tagECC = Some("parity"), 331 dataECC = Some("parity"), 332 replacer = Some("setplru"), 333 ), 334 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 335 tagECC = Some("secded"), 336 dataECC = Some("secded"), 337 replacer = Some("setplru"), 338 nMissEntries = 16, 339 nProbeEntries = 8, 340 nReleaseEntries = 18, 341 nMaxPrefetchEntry = 6, 342 )), 343 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 344 name = "l2", 345 ways = 8, 346 sets = 1024, // default 512KB L2 347 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 348 coupledL2.prefetch.TPParameters()), 349 )), 350 L2NBanks: Int = 1, 351 usePTWRepeater: Boolean = false, 352 softTLB: Boolean = false, // dpi-c l1tlb debug only 353 softPTW: Boolean = false, // dpi-c l2tlb debug only 354 softPTWDelay: Int = 1 355){ 356 def vlWidth = log2Up(VLEN) + 1 357 358 /** 359 * the minimum element length of vector elements 360 */ 361 val minVecElen: Int = 8 362 363 /** 364 * the maximum number of elements in vector register 365 */ 366 val maxElemPerVreg: Int = VLEN / minVecElen 367 368 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 369 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 370 371 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 372 val RegCacheIdxWidth = log2Up(RegCacheSize) 373 374 val intSchdParams = { 375 implicit val schdType: SchedulerType = IntScheduler() 376 SchdBlockParams(Seq( 377 IssueBlockParams(Seq( 378 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 379 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 380 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 381 IssueBlockParams(Seq( 382 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 383 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 384 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 385 IssueBlockParams(Seq( 386 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 387 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 388 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 389 IssueBlockParams(Seq( 390 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 391 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 ), 394 numPregs = intPreg.numEntries, 395 numDeqOutside = 0, 396 schdType = schdType, 397 rfDataWidth = intPreg.dataCfg.dataWidth, 398 numUopIn = dpParams.IntDqDeqWidth, 399 ) 400 } 401 402 val fpSchdParams = { 403 implicit val schdType: SchedulerType = FpScheduler() 404 SchdBlockParams(Seq( 405 IssueBlockParams(Seq( 406 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 407 ), numEntries = 18, numEnq = 2, numComp = 16), 408 IssueBlockParams(Seq( 409 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 410 ), numEntries = 18, numEnq = 2, numComp = 16), 411 IssueBlockParams(Seq( 412 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 413 ), numEntries = 18, numEnq = 2, numComp = 16), 414 IssueBlockParams(Seq( 415 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 416 ), numEntries = 18, numEnq = 2, numComp = 16), 417 IssueBlockParams(Seq( 418 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 419 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 420 ), numEntries = 18, numEnq = 2, numComp = 16), 421 ), 422 numPregs = fpPreg.numEntries, 423 numDeqOutside = 0, 424 schdType = schdType, 425 rfDataWidth = fpPreg.dataCfg.dataWidth, 426 numUopIn = dpParams.VecDqDeqWidth, 427 ) 428 } 429 430 val vfSchdParams = { 431 implicit val schdType: SchedulerType = VfScheduler() 432 SchdBlockParams(Seq( 433 IssueBlockParams(Seq( 434 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 435 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 436 ), numEntries = 16, numEnq = 2, numComp = 14), 437 IssueBlockParams(Seq( 438 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 439 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 440 ), numEntries = 16, numEnq = 2, numComp = 14), 441 IssueBlockParams(Seq( 442 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 443 ), numEntries = 10, numEnq = 2, numComp = 8), 444 ), 445 numPregs = vfPreg.numEntries, 446 numDeqOutside = 0, 447 schdType = schdType, 448 rfDataWidth = vfPreg.dataCfg.dataWidth, 449 numUopIn = dpParams.VecDqDeqWidth, 450 ) 451 } 452 453 val memSchdParams = { 454 implicit val schdType: SchedulerType = MemScheduler() 455 val rfDataWidth = 64 456 457 SchdBlockParams(Seq( 458 IssueBlockParams(Seq( 459 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 463 ), numEntries = 16, numEnq = 2, numComp = 14), 464 IssueBlockParams(Seq( 465 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 466 ), numEntries = 16, numEnq = 2, numComp = 14), 467 IssueBlockParams(Seq( 468 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 469 ), numEntries = 16, numEnq = 2, numComp = 14), 470 IssueBlockParams(Seq( 471 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 472 ), numEntries = 16, numEnq = 2, numComp = 14), 473 IssueBlockParams(Seq( 474 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 475 ), numEntries = 16, numEnq = 2, numComp = 14), 476 IssueBlockParams(Seq( 477 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 478 ), numEntries = 16, numEnq = 2, numComp = 14), 479 IssueBlockParams(Seq( 480 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 481 ), numEntries = 16, numEnq = 2, numComp = 14), 482 IssueBlockParams(Seq( 483 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 484 ), numEntries = 16, numEnq = 2, numComp = 14), 485 ), 486 numPregs = intPreg.numEntries max vfPreg.numEntries, 487 numDeqOutside = 0, 488 schdType = schdType, 489 rfDataWidth = rfDataWidth, 490 numUopIn = dpParams.LsDqDeqWidth, 491 ) 492 } 493 494 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 495 496 def iqWakeUpParams = { 497 Seq( 498 WakeUpConfig( 499 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 500 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 501 ), 502 // TODO: add load -> fp slow wakeup 503 WakeUpConfig( 504 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 505 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 506 ), 507 WakeUpConfig( 508 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 509 Seq("STD0", "STD1") 510 ), 511// WakeUpConfig( 512// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 513// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 514// ), 515 ).flatten 516 } 517 518 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 519 520 val backendParams: BackendParams = backend.BackendParams( 521 Map( 522 IntScheduler() -> intSchdParams, 523 FpScheduler() -> fpSchdParams, 524 VfScheduler() -> vfSchdParams, 525 MemScheduler() -> memSchdParams, 526 ), 527 Seq( 528 intPreg, 529 fpPreg, 530 vfPreg, 531 v0Preg, 532 vlPreg, 533 fakeIntPreg 534 ), 535 iqWakeUpParams, 536 ) 537 538 // Parameters for trace extension. 539 // Trace parameters is useful for XSTOP. 540 val TraceGroupNum = 3 // Width to Encoder 541} 542 543case object DebugOptionsKey extends Field[DebugOptions] 544 545case class DebugOptions 546( 547 FPGAPlatform: Boolean = false, 548 ResetGen: Boolean = false, 549 EnableDifftest: Boolean = false, 550 AlwaysBasicDiff: Boolean = true, 551 EnableDebug: Boolean = false, 552 EnablePerfDebug: Boolean = true, 553 UseDRAMSim: Boolean = false, 554 EnableConstantin: Boolean = false, 555 EnableChiselDB: Boolean = false, 556 AlwaysBasicDB: Boolean = true, 557 EnableRollingDB: Boolean = false 558) 559 560trait HasXSParameter { 561 562 implicit val p: Parameters 563 564 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 565 final val PageOffsetWidth = 12 566 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 567 568 def coreParams = p(XSCoreParamsKey) 569 def env = p(DebugOptionsKey) 570 571 def XLEN = coreParams.XLEN 572 def VLEN = coreParams.VLEN 573 def ELEN = coreParams.ELEN 574 def HSXLEN = coreParams.HSXLEN 575 val minFLen = 32 576 val fLen = 64 577 def hartIdLen = p(MaxHartIdBits) 578 val xLen = XLEN 579 580 def HasMExtension = coreParams.HasMExtension 581 def HasCExtension = coreParams.HasCExtension 582 def HasHExtension = coreParams.HasHExtension 583 def EnableSv48 = coreParams.EnableSv48 584 def HasDiv = coreParams.HasDiv 585 def HasIcache = coreParams.HasICache 586 def HasDcache = coreParams.HasDCache 587 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 588 def GPAddrBits = { 589 if (EnableSv48) 590 coreParams.GPAddrBitsSv48x4 591 else 592 coreParams.GPAddrBitsSv39x4 593 } 594 def VAddrBits = { 595 if (HasHExtension) { 596 if (EnableSv48) 597 coreParams.GPAddrBitsSv48x4 598 else 599 coreParams.GPAddrBitsSv39x4 600 } else { 601 if (EnableSv48) 602 coreParams.VAddrBitsSv48 603 else 604 coreParams.VAddrBitsSv39 605 } 606 } // VAddrBits is Virtual Memory addr bits 607 require(PAddrBits == 48 || !EnableSv48) // Paddr bits should be 48 when Sv48 enable 608 609 def VAddrMaxBits = { 610 if(EnableSv48) { 611 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 612 } else { 613 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 614 } 615 } 616 617 def AsidLength = coreParams.AsidLength 618 def VmidLength = coreParams.VmidLength 619 def ReSelectLen = coreParams.ReSelectLen 620 def AddrBytes = AddrBits / 8 // unused 621 def DataBits = XLEN 622 def DataBytes = DataBits / 8 623 def VDataBytes = VLEN / 8 624 def HasFPU = coreParams.HasFPU 625 def HasVPU = coreParams.HasVPU 626 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 627 def FetchWidth = coreParams.FetchWidth 628 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 629 def EnableBPU = coreParams.EnableBPU 630 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 631 def EnableRAS = coreParams.EnableRAS 632 def EnableLB = coreParams.EnableLB 633 def EnableLoop = coreParams.EnableLoop 634 def EnableSC = coreParams.EnableSC 635 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 636 def HistoryLength = coreParams.HistoryLength 637 def EnableGHistDiff = coreParams.EnableGHistDiff 638 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 639 def EnableClockGate = coreParams.EnableClockGate 640 def UbtbGHRLength = coreParams.UbtbGHRLength 641 def UbtbSize = coreParams.UbtbSize 642 def EnableFauFTB = coreParams.EnableFauFTB 643 def FtbSize = coreParams.FtbSize 644 def FtbWays = coreParams.FtbWays 645 def RasSize = coreParams.RasSize 646 def RasSpecSize = coreParams.RasSpecSize 647 def RasCtrSize = coreParams.RasCtrSize 648 649 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 650 coreParams.branchPredictor(resp_in, p) 651 } 652 def numBr = coreParams.numBr 653 def TageTableInfos = coreParams.TageTableInfos 654 def TageBanks = coreParams.numBr 655 def SCNRows = coreParams.SCNRows 656 def SCCtrBits = coreParams.SCCtrBits 657 def SCHistLens = coreParams.SCHistLens 658 def SCNTables = coreParams.SCNTables 659 660 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 661 case ((n, cb), h) => (n, cb, h) 662 } 663 def ITTageTableInfos = coreParams.ITTageTableInfos 664 type FoldedHistoryInfo = Tuple2[Int, Int] 665 def foldedGHistInfos = 666 (TageTableInfos.map{ case (nRows, h, t) => 667 if (h > 0) 668 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 669 else 670 Set[FoldedHistoryInfo]() 671 }.reduce(_++_).toSet ++ 672 SCTableInfos.map{ case (nRows, _, h) => 673 if (h > 0) 674 Set((h, min(log2Ceil(nRows/TageBanks), h))) 675 else 676 Set[FoldedHistoryInfo]() 677 }.reduce(_++_).toSet ++ 678 ITTageTableInfos.map{ case (nRows, h, t) => 679 if (h > 0) 680 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 681 else 682 Set[FoldedHistoryInfo]() 683 }.reduce(_++_) ++ 684 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 685 ).toList 686 687 688 689 def CacheLineSize = coreParams.CacheLineSize 690 def CacheLineHalfWord = CacheLineSize / 16 691 def ExtHistoryLength = HistoryLength + 64 692 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 693 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 694 def IBufSize = coreParams.IBufSize 695 def IBufNBank = coreParams.IBufNBank 696 def backendParams: BackendParams = coreParams.backendParams 697 def DecodeWidth = coreParams.DecodeWidth 698 def RenameWidth = coreParams.RenameWidth 699 def CommitWidth = coreParams.CommitWidth 700 def RobCommitWidth = coreParams.RobCommitWidth 701 def RabCommitWidth = coreParams.RabCommitWidth 702 def MaxUopSize = coreParams.MaxUopSize 703 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 704 def RenameSnapshotNum = coreParams.RenameSnapshotNum 705 def FtqSize = coreParams.FtqSize 706 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 707 def IntLogicRegs = coreParams.IntLogicRegs 708 def FpLogicRegs = coreParams.FpLogicRegs 709 def VecLogicRegs = coreParams.VecLogicRegs 710 def V0LogicRegs = coreParams.V0LogicRegs 711 def VlLogicRegs = coreParams.VlLogicRegs 712 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 713 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 714 def V0_IDX = coreParams.V0_IDX 715 def Vl_IDX = coreParams.Vl_IDX 716 def IntPhyRegs = coreParams.intPreg.numEntries 717 def FpPhyRegs = coreParams.fpPreg.numEntries 718 def VfPhyRegs = coreParams.vfPreg.numEntries 719 def V0PhyRegs = coreParams.v0Preg.numEntries 720 def VlPhyRegs = coreParams.vlPreg.numEntries 721 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 722 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 723 def RobSize = coreParams.RobSize 724 def RabSize = coreParams.RabSize 725 def VTypeBufferSize = coreParams.VTypeBufferSize 726 def IntRegCacheSize = coreParams.IntRegCacheSize 727 def MemRegCacheSize = coreParams.MemRegCacheSize 728 def RegCacheSize = coreParams.RegCacheSize 729 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 730 /** 731 * the minimum element length of vector elements 732 */ 733 def minVecElen: Int = coreParams.minVecElen 734 735 /** 736 * the maximum number of elements in vector register 737 */ 738 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 739 740 def IntRefCounterWidth = log2Ceil(RobSize) 741 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 742 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 743 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 744 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 745 def LoadQueueRARSize = coreParams.LoadQueueRARSize 746 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 747 def RollbackGroupSize = coreParams.RollbackGroupSize 748 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 749 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 750 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 751 def StoreQueueSize = coreParams.StoreQueueSize 752 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 753 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 754 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 755 def VlsQueueSize = coreParams.VlsQueueSize 756 def dpParams = coreParams.dpParams 757 758 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 759 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 760 761 def NumRedirect = backendParams.numRedirect 762 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 763 def FtqRedirectAheadNum = NumRedirect 764 def IfuRedirectNum = coreParams.IfuRedirectNum 765 def LoadPipelineWidth = coreParams.LoadPipelineWidth 766 def StorePipelineWidth = coreParams.StorePipelineWidth 767 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 768 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 769 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 770 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 771 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 772 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 773 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 774 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 775 def StoreBufferSize = coreParams.StoreBufferSize 776 def StoreBufferThreshold = coreParams.StoreBufferThreshold 777 def EnsbufferWidth = coreParams.EnsbufferWidth 778 def LoadDependencyWidth = coreParams.LoadDependencyWidth 779 def VlMergeBufferSize = coreParams.VlMergeBufferSize 780 def VsMergeBufferSize = coreParams.VsMergeBufferSize 781 def UopWritebackWidth = coreParams.UopWritebackWidth 782 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 783 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 784 def VSegmentBufferSize = coreParams.VSegmentBufferSize 785 def UncacheBufferSize = coreParams.UncacheBufferSize 786 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 787 def EnableFastForward = coreParams.EnableFastForward 788 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 789 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 790 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 791 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 792 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 793 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 794 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 795 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 796 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 797 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 798 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 799 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 800 def HasRVA23CMO = coreParams.HasRVA23CMO 801 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 802 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 803 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 804 def asidLen = coreParams.MMUAsidLen 805 def vmidLen = coreParams.MMUVmidLen 806 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 807 def refillBothTlb = coreParams.refillBothTlb 808 def iwpuParam = coreParams.iwpuParameters 809 def dwpuParam = coreParams.dwpuParameters 810 def itlbParams = coreParams.itlbParameters 811 def ldtlbParams = coreParams.ldtlbParameters 812 def sttlbParams = coreParams.sttlbParameters 813 def hytlbParams = coreParams.hytlbParameters 814 def pftlbParams = coreParams.pftlbParameters 815 def l2ToL1Params = coreParams.l2ToL1tlbParameters 816 def btlbParams = coreParams.btlbParameters 817 def l2tlbParams = coreParams.l2tlbParameters 818 def NumPerfCounters = coreParams.NumPerfCounters 819 820 def instBytes = if (HasCExtension) 2 else 4 821 def instOffsetBits = log2Ceil(instBytes) 822 823 def icacheParameters = coreParams.icacheParameters 824 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 825 826 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 827 // for constrained LR/SC loop 828 def LRSCCycles = 64 829 // for lr storm 830 def LRSCBackOff = 8 831 832 // cache hierarchy configurations 833 def l1BusDataWidth = 256 834 835 // load violation predict 836 def ResetTimeMax2Pow = 20 //1078576 837 def ResetTimeMin2Pow = 10 //1024 838 // wait table parameters 839 def WaitTableSize = 1024 840 def MemPredPCWidth = log2Up(WaitTableSize) 841 def LWTUse2BitCounter = true 842 // store set parameters 843 def SSITSize = WaitTableSize 844 def LFSTSize = 32 845 def SSIDWidth = log2Up(LFSTSize) 846 def LFSTWidth = 4 847 def StoreSetEnable = true // LWT will be disabled if SS is enabled 848 def LFSTEnable = true 849 850 def PCntIncrStep: Int = 6 851 def numPCntHc: Int = 25 852 def numPCntPtw: Int = 19 853 854 def numCSRPCntFrontend = 8 855 def numCSRPCntCtrl = 8 856 def numCSRPCntLsu = 8 857 def numCSRPCntHc = 5 858 def printEventCoding = true 859 860 // Parameters for Sdtrig extension 861 protected def TriggerNum = 4 862 protected def TriggerChainMaxLength = 2 863 864 // Parameters for Trace extension 865 def TraceGroupNum = coreParams.TraceGroupNum 866} 867