1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.backend.fu.NewCSR._ 32import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 33import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 34 35class StoreUnit(implicit p: Parameters) extends XSModule 36 with HasDCacheParameters 37 with HasVLSUParameters 38 { 39 val io = IO(new Bundle() { 40 val redirect = Flipped(ValidIO(new Redirect)) 41 val stin = Flipped(Decoupled(new MemExuInput)) 42 val issue = Valid(new MemExuInput) 43 val tlb = new TlbRequestIO() 44 val dcache = new DCacheStoreIO 45 val pmp = Flipped(new PMPRespBundle()) 46 val lsq = ValidIO(new LsPipelineBundle) 47 val lsq_replenish = Output(new LsPipelineBundle()) 48 val feedback_slow = ValidIO(new RSFeedback) 49 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 50 // provide prefetch info to sms 51 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 52 // speculative for gated control 53 val s1_prefetch_spec = Output(Bool()) 54 val s2_prefetch_spec = Output(Bool()) 55 val stld_nuke_query = Valid(new StoreNukeQueryIO) 56 val stout = DecoupledIO(new MemExuOutput) // writeback store 57 val vecstout = DecoupledIO(new VecPipelineFeedbackIO(isVStore = true)) 58 // store mask, send to sq in store_s0 59 val st_mask_out = Valid(new StoreMaskBundle) 60 val debug_ls = Output(new DebugLsInfoBundle) 61 // vector 62 val vecstin = Flipped(Decoupled(new VecPipeBundle(isVStore = true))) 63 val vec_isFirstIssue = Input(Bool()) 64 // trigger 65 val fromCsrTrigger = Input(new CsrTriggerBundle) 66 }) 67 68 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 69 70 // Pipeline 71 // -------------------------------------------------------------------------------- 72 // stage 0 73 // -------------------------------------------------------------------------------- 74 // generate addr, use addr to query DCache and DTLB 75 val s0_iss_valid = io.stin.valid 76 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 77 val s0_vec_valid = io.vecstin.valid 78 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid 79 val s0_use_flow_vec = s0_vec_valid 80 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid 81 val s0_use_flow_prf = !s0_iss_valid && !s0_vec_valid && s0_prf_valid 82 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 83 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 84 val s0_uop = Mux(s0_use_flow_rs, s0_stin.uop, s0_vecstin.uop) 85 val s0_isFirstIssue = s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 86 val s0_size = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature 87 val s0_mem_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.sqIdx.value, 0.U) 88 val s0_rob_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 89 val s0_pc = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.pc, 0.U) 90 val s0_instr_type = Mux(s0_use_flow_rs || s0_use_flow_vec, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 91 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 92 val s0_out = Wire(new LsPipelineBundle) 93 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 94 val s0_can_go = s1_ready 95 val s0_fire = s0_valid && !s0_kill && s0_can_go 96 val s0_is128bit = is128Bit(s0_vecstin.alignedType) 97 // vector 98 val s0_vecActive = !s0_use_flow_vec || s0_vecstin.vecActive 99 // val s0_flowPtr = s0_vecstin.flowPtr 100 // val s0_isLastElem = s0_vecstin.isLastElem 101 val s0_secondInv = s0_vecstin.usSecondInv 102 val s0_elemIdx = s0_vecstin.elemIdx 103 val s0_alignedType = s0_vecstin.alignedType 104 val s0_mBIndex = s0_vecstin.mBIndex 105 106 // generate addr 107 val s0_saddr = s0_stin.src(0) + SignExt(s0_uop.imm(11,0), VAddrBits) 108 val s0_vaddr = Mux( 109 s0_use_flow_rs, 110 s0_saddr, 111 Mux( 112 s0_use_flow_vec, 113 s0_vecstin.vaddr, 114 io.prefetch_req.bits.vaddr 115 ) 116 ) 117 val s0_mask = Mux( 118 s0_use_flow_rs, 119 genVWmask128(s0_saddr, s0_uop.fuOpType(2,0)), 120 Mux( 121 s0_use_flow_vec, 122 s0_vecstin.mask, 123 // -1.asSInt.asUInt 124 Fill(VLEN/8, 1.U(1.W)) 125 ) 126 ) 127 128 io.tlb.req.valid := s0_valid 129 io.tlb.req.bits.vaddr := s0_vaddr 130 io.tlb.req.bits.cmd := TlbCmd.write 131 io.tlb.req.bits.size := s0_size 132 io.tlb.req.bits.kill := false.B 133 io.tlb.req.bits.memidx.is_ld := false.B 134 io.tlb.req.bits.memidx.is_st := true.B 135 io.tlb.req.bits.memidx.idx := s0_mem_idx 136 io.tlb.req.bits.debug.robIdx := s0_rob_idx 137 io.tlb.req.bits.no_translate := false.B 138 io.tlb.req.bits.debug.pc := s0_pc 139 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 140 io.tlb.req_kill := false.B 141 io.tlb.req.bits.hyperinst := LSUOpType.isHsv(s0_uop.fuOpType) 142 io.tlb.req.bits.hlvx := false.B 143 144 // Dcache access here: not **real** dcache write 145 // just read meta and tag in dcache, to find out the store will hit or miss 146 147 // NOTE: The store request does not wait for the dcache to be ready. 148 // If the dcache is not ready at this time, the dcache is not queried. 149 // But, store prefetch request will always wait for dcache to be ready to make progress. 150 io.dcache.req.valid := s0_fire 151 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 152 io.dcache.req.bits.vaddr := s0_vaddr 153 io.dcache.req.bits.instrtype := s0_instr_type 154 155 s0_out := DontCare 156 s0_out.vaddr := s0_vaddr 157 // Now data use its own io 158 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 159 s0_out.data := s0_stin.src(1) 160 s0_out.uop := s0_uop 161 s0_out.miss := false.B 162 s0_out.mask := s0_mask 163 s0_out.isFirstIssue := s0_isFirstIssue 164 s0_out.isHWPrefetch := s0_use_flow_prf 165 s0_out.wlineflag := s0_wlineflag 166 s0_out.isvec := s0_use_flow_vec 167 s0_out.is128bit := s0_is128bit 168 s0_out.vecActive := s0_vecActive 169 s0_out.usSecondInv := s0_secondInv 170 s0_out.elemIdx := s0_elemIdx 171 s0_out.alignedType := s0_alignedType 172 s0_out.mbIndex := s0_mBIndex 173 when(s0_valid && s0_isFirstIssue) { 174 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 175 } 176 177 // exception check 178 val s0_addr_aligned = LookupTree(Mux(s0_use_flow_vec, s0_vecstin.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 179 "b00".U -> true.B, //b 180 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 181 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 182 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 183 )) 184 // if vector store sends 128-bit requests, its address must be 128-aligned 185 XSError(s0_use_flow_vec && s0_out.vaddr(3, 0) =/= 0.U && s0_vecstin.alignedType(2), "unit stride 128 bit element is not aligned!") 186 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs || s0_use_flow_vec, !s0_addr_aligned, false.B) 187 188 io.st_mask_out.valid := s0_use_flow_rs || s0_use_flow_vec 189 io.st_mask_out.bits.mask := s0_out.mask 190 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 191 192 io.stin.ready := s1_ready && s0_use_flow_rs 193 io.vecstin.ready := s1_ready && s0_use_flow_vec 194 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid 195 196 // Pipeline 197 // -------------------------------------------------------------------------------- 198 // stage 1 199 // -------------------------------------------------------------------------------- 200 // TLB resp (send paddr to dcache) 201 val s1_valid = RegInit(false.B) 202 val s1_in = RegEnable(s0_out, s0_fire) 203 val s1_out = Wire(new LsPipelineBundle) 204 val s1_kill = Wire(Bool()) 205 val s1_can_go = s2_ready 206 val s1_fire = s1_valid && !s1_kill && s1_can_go 207 val s1_vecActive = RegEnable(s0_out.vecActive, true.B, s0_fire) 208 209 // mmio cbo decoder 210 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 211 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 212 s1_in.uop.fuOpType === LSUOpType.cbo_inval 213 val s1_paddr = io.tlb.resp.bits.paddr(0) 214 val s1_gpaddr = io.tlb.resp.bits.gpaddr(0) 215 val s1_tlb_miss = io.tlb.resp.bits.miss 216 val s1_mmio = s1_mmio_cbo 217 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 218 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 219 // val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 220 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || (s1_tlb_miss && !s1_isvec) 221 222 s1_ready := !s1_valid || s1_kill || s2_ready 223 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 224 when (s0_fire) { s1_valid := true.B } 225 .elsewhen (s1_fire) { s1_valid := false.B } 226 .elsewhen (s1_kill) { s1_valid := false.B } 227 228 // st-ld violation dectect request. 229 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 230 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 231 io.stld_nuke_query.bits.paddr := s1_paddr 232 io.stld_nuke_query.bits.mask := s1_in.mask 233 io.stld_nuke_query.bits.matchLine := s1_in.isvec && s1_in.is128bit 234 235 // issue 236 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec 237 io.issue.bits := RegEnable(s0_stin, s0_valid) 238 239 240 // Send TLB feedback to store issue queue 241 // Store feedback is generated in store_s1, sent to RS in store_s2 242 val s1_feedback = Wire(Valid(new RSFeedback)) 243 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 244 s1_feedback.bits.hit := !s1_tlb_miss 245 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 246 s1_feedback.bits.robIdx := s1_out.uop.robIdx 247 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 248 s1_feedback.bits.dataInvalidSqIdx := DontCare 249 s1_feedback.bits.sqIdx := s1_out.uop.sqIdx 250 s1_feedback.bits.lqIdx := s1_out.uop.lqIdx 251 252 XSDebug(s1_feedback.valid, 253 "S1 Store: tlbHit: %d robIdx: %d\n", 254 s1_feedback.bits.hit, 255 s1_feedback.bits.robIdx.value 256 ) 257 258 // io.feedback_slow := s1_feedback 259 260 // get paddr from dtlb, check if rollback is needed 261 // writeback store inst to lsq 262 s1_out := s1_in 263 s1_out.paddr := s1_paddr 264 s1_out.gpaddr := s1_gpaddr 265 s1_out.miss := false.B 266 s1_out.mmio := s1_mmio 267 s1_out.tlbMiss := s1_tlb_miss 268 s1_out.atomic := s1_mmio 269 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_vecActive 270 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_vecActive 271 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st && s1_vecActive 272 273 // trigger 274 val storeTrigger = Module(new StoreTrigger) 275 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 276 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 277 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 278 storeTrigger.io.fromStore.vaddr := s1_in.vaddr 279 280 s1_out.uop.trigger.backendHit := storeTrigger.io.toStore.triggerHitVec 281 s1_out.uop.trigger.backendCanFire := storeTrigger.io.toStore.triggerCanFireVec 282 s1_out.uop.exceptionVec(breakPoint) := storeTrigger.io.toStore.breakPointExp 283 284 // scalar store and scalar load nuke check, and also other purposes 285 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 286 io.lsq.bits := s1_out 287 io.lsq.bits.miss := s1_tlb_miss 288 289 // kill dcache write intent request when tlb miss or exception 290 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 291 io.dcache.s1_paddr := s1_paddr 292 293 // write below io.out.bits assign sentence to prevent overwriting values 294 val s1_tlb_memidx = io.tlb.resp.bits.memidx 295 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 296 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 297 s1_out.uop.debugInfo.tlbRespTime := GTimer() 298 } 299 300 // Pipeline 301 // -------------------------------------------------------------------------------- 302 // stage 2 303 // -------------------------------------------------------------------------------- 304 // mmio check 305 val s2_valid = RegInit(false.B) 306 val s2_in = RegEnable(s1_out, s1_fire) 307 val s2_out = Wire(new LsPipelineBundle) 308 val s2_kill = Wire(Bool()) 309 val s2_can_go = s3_ready 310 val s2_fire = s2_valid && !s2_kill && s2_can_go 311 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 312 313 s2_ready := !s2_valid || s2_kill || s3_ready 314 when (s1_fire) { s2_valid := true.B } 315 .elsewhen (s2_fire) { s2_valid := false.B } 316 .elsewhen (s2_kill) { s2_valid := false.B } 317 318 val s2_pmp = WireInit(io.pmp) 319 320 val s2_exception = (ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR) && RegNext(s1_feedback.bits.hit) 321 val s2_mmio = (s2_in.mmio || s2_pmp.mmio) && RegNext(s1_feedback.bits.hit) 322 s2_kill := ((s2_mmio && !s2_exception) && !s2_in.isvec) || s2_in.uop.robIdx.needFlush(io.redirect) 323 324 s2_out := s2_in 325 s2_out.af := s2_pmp.st && !s2_in.isvec 326 s2_out.mmio := s2_mmio && !s2_exception 327 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 328 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || 329 s2_pmp.st || 330 (s2_in.isvec && s2_pmp.mmio && RegNext(s1_feedback.bits.hit)) 331 ) && s2_vecActive 332 333 // kill dcache write intent request when mmio or exception 334 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 335 io.dcache.s2_pc := s2_out.uop.pc 336 // TODO: dcache resp 337 io.dcache.resp.ready := true.B 338 339 // feedback tlb miss to RS in store_s2 340 val feedback_slow_valid = WireInit(false.B) 341 feedback_slow_valid := s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect) && !s1_out.isvec 342 io.feedback_slow.valid := GatedValidRegNext(feedback_slow_valid) 343 io.feedback_slow.bits := RegEnable(s1_feedback.bits, feedback_slow_valid) 344 345 val s2_vecFeedback = RegNext(!s1_out.uop.robIdx.needFlush(io.redirect) && s1_feedback.bits.hit) && s2_in.isvec 346 347 // mmio and exception 348 io.lsq_replenish := s2_out 349 io.lsq_replenish.af := s2_out.af && !s2_kill 350 351 // prefetch related 352 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 353 354 // RegNext prefetch train for better timing 355 // ** Now, prefetch train is valid at store s3 ** 356 val s2_prefetch_train_valid = WireInit(false.B) 357 s2_prefetch_train_valid := s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch 358 if(EnableStorePrefetchSMS) { 359 io.s1_prefetch_spec := s1_fire 360 io.s2_prefetch_spec := s2_prefetch_train_valid 361 io.prefetch_train.valid := RegNext(s2_prefetch_train_valid) 362 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = s2_prefetch_train_valid) 363 }else { 364 io.s1_prefetch_spec := false.B 365 io.s2_prefetch_spec := false.B 366 io.prefetch_train.valid := false.B 367 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = false.B) 368 } 369 // override miss bit 370 io.prefetch_train.bits.miss := RegEnable(io.dcache.resp.bits.miss, s2_prefetch_train_valid) 371 // TODO: add prefetch and access bit 372 io.prefetch_train.bits.meta_prefetch := false.B 373 io.prefetch_train.bits.meta_access := false.B 374 375 // Pipeline 376 // -------------------------------------------------------------------------------- 377 // stage 3 378 // -------------------------------------------------------------------------------- 379 // store write back 380 val s3_valid = RegInit(false.B) 381 val s3_in = RegEnable(s2_out, s2_fire) 382 val s3_out = Wire(new MemExuOutput(isVector = true)) 383 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 384 val s3_can_go = s3_ready 385 val s3_fire = s3_valid && !s3_kill && s3_can_go 386 val s3_vecFeedback = RegEnable(s2_vecFeedback, s2_fire) 387 388 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 389 .elsewhen (s3_fire) { s3_valid := false.B } 390 .elsewhen (s3_kill) { s3_valid := false.B } 391 392 // wb: writeback 393 val SelectGroupSize = RollbackGroupSize 394 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 395 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 396 397 s3_out := DontCare 398 s3_out.uop := s3_in.uop 399 s3_out.data := DontCare 400 s3_out.debug.isMMIO := s3_in.mmio 401 s3_out.debug.paddr := s3_in.paddr 402 s3_out.debug.vaddr := s3_in.vaddr 403 s3_out.debug.isPerfCnt := false.B 404 405 // Pipeline 406 // -------------------------------------------------------------------------------- 407 // stage x 408 // -------------------------------------------------------------------------------- 409 // delay TotalSelectCycles - 2 cycle(s) 410 val TotalDelayCycles = TotalSelectCycles - 2 411 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 412 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 413 val sx_in = Wire(Vec(TotalDelayCycles + 1, new VecMemExuOutput(isVector = true))) 414 415 // backward ready signal 416 s3_ready := sx_ready.head 417 for (i <- 0 until TotalDelayCycles + 1) { 418 if (i == 0) { 419 sx_valid(i) := s3_valid 420 sx_in(i).output := s3_out 421 sx_in(i).vecFeedback := s3_vecFeedback 422 sx_in(i).mmio := s3_in.mmio 423 sx_in(i).usSecondInv := s3_in.usSecondInv 424 sx_in(i).elemIdx := s3_in.elemIdx 425 sx_in(i).alignedType := s3_in.alignedType 426 sx_in(i).mbIndex := s3_in.mbIndex 427 sx_in(i).mask := s3_in.mask 428 sx_in(i).vaddr := s3_in.vaddr 429 sx_ready(i) := !s3_valid(i) || sx_in(i).output.uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 430 } else { 431 val cur_kill = sx_in(i).output.uop.robIdx.needFlush(io.redirect) 432 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 433 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 434 val prev_fire = sx_valid(i-1) && !sx_in(i-1).output.uop.robIdx.needFlush(io.redirect) && sx_ready(i) 435 436 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 437 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 438 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 439 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 440 } 441 } 442 val sx_last_valid = sx_valid.takeRight(1).head 443 val sx_last_ready = sx_ready.takeRight(1).head 444 val sx_last_in = sx_in.takeRight(1).head 445 sx_last_ready := !sx_last_valid || sx_last_in.output.uop.robIdx.needFlush(io.redirect) || io.stout.ready 446 447 io.stout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isStore(sx_last_in.output.uop.fuType) 448 io.stout.bits := sx_last_in.output 449 io.stout.bits.uop.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, StaCfg) 450 451 io.vecstout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isVStore(sx_last_in.output.uop.fuType) 452 // TODO: implement it! 453 io.vecstout.bits.mBIndex := sx_last_in.mbIndex 454 io.vecstout.bits.hit := sx_last_in.vecFeedback 455 io.vecstout.bits.isvec := true.B 456 io.vecstout.bits.sourceType := RSFeedbackType.tlbMiss 457 io.vecstout.bits.flushState := DontCare 458 io.vecstout.bits.mmio := sx_last_in.mmio 459 io.vecstout.bits.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, VstuCfg) 460 io.vecstout.bits.usSecondInv := sx_last_in.usSecondInv 461 io.vecstout.bits.vecFeedback := sx_last_in.vecFeedback 462 io.vecstout.bits.elemIdx := sx_last_in.elemIdx 463 io.vecstout.bits.alignedType := sx_last_in.alignedType 464 io.vecstout.bits.mask := sx_last_in.mask 465 io.vecstout.bits.vaddr := sx_last_in.vaddr 466 // io.vecstout.bits.reg_offset.map(_ := DontCare) 467 // io.vecstout.bits.elemIdx.map(_ := sx_last_in.elemIdx) 468 // io.vecstout.bits.elemIdxInsideVd.map(_ := DontCare) 469 // io.vecstout.bits.vecdata.map(_ := DontCare) 470 // io.vecstout.bits.mask.map(_ := DontCare) 471 // io.vecstout.bits.alignedType.map(_ := sx_last_in.alignedType) 472 473 io.debug_ls := DontCare 474 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 475 io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 476 477 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 478 XSDebug(cond, 479 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 480 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 481 p"op ${Binary(pipeline.uop.fuOpType)} " + 482 p"data ${Hexadecimal(pipeline.data)} " + 483 p"mask ${Hexadecimal(pipeline.mask)}\n" 484 ) 485 } 486 487 printPipeLine(s0_out, s0_valid, "S0") 488 printPipeLine(s1_out, s1_valid, "S1") 489 490 // perf cnt 491 XSPerfAccumulate("s0_in_valid", s0_valid) 492 XSPerfAccumulate("s0_in_fire", s0_fire) 493 XSPerfAccumulate("s0_vecin_fire", s0_fire && s0_use_flow_vec) 494 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 495 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 496 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 497 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 498 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 499 500 XSPerfAccumulate("s1_in_valid", s1_valid) 501 XSPerfAccumulate("s1_in_fire", s1_fire) 502 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 503 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 504 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 505 // end 506}