| #
d082eb24 |
| 14-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: "-" has a higher priority than "<<"
|
| #
e299e123 |
| 14-Jul-2020 |
GouLingrui <[email protected]> |
BPU: rebase btb with 16 banks, can pass 12/33 cputests
|
| #
f36655eb |
| 13-Jul-2020 |
zhanglinjuan <[email protected]> |
btb: add read and write bypass
|
| #
2445e0c0 |
| 13-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: block Stage2 when Stage3 is blocked
|
| #
2a39fd19 |
| 13-Jul-2020 |
ZhangZifei <[email protected]> |
BPU: add Tage's Perf Cnt
|
| #
55fe8440 |
| 12-Jul-2020 |
GouLingrui <[email protected]> |
Merge remote-tracking branch 'origin/dev-bpu-pipe-pc' into dev-bpu-pipeline
|
| #
f8f3cce1 |
| 12-Jul-2020 |
GouLingrui <[email protected]> |
split jbtac into independent file
|
| #
d5aa97e2 |
| 12-Jul-2020 |
GouLingrui <[email protected]> |
split btb and add logic for situations in which btb need not be updated
|
| #
7f4773ba |
| 12-Jul-2020 |
ZhangZifei <[email protected]> |
Merge branch 'dev-bpu-pipeline' into dev-bpu-pipe-pc
|
| #
b5f5fbe6 |
| 12-Jul-2020 |
ZhangZifei <[email protected]> |
BPU: add temp perf counter
|
| #
1891fed5 |
| 12-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: reverse "Cat" result of Seq type
ibuffer: fix io.in.ready to "!full"
|
| #
bd4fe2ff |
| 11-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: fix flush signal in BPUStage1
|
| #
5c2a827e |
| 11-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: fix io.out.bits.redirect in BPUStage3
|
| #
cceb7f67 |
| 10-Jul-2020 |
GouLingrui <[email protected]> |
Get TAGE working
|
| #
e52686f8 |
| 10-Jul-2020 |
zhanglinjuan <[email protected]> |
ifu: add redirectInfo into bpu
|
| #
5113dcfa |
| 10-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: fix NotInitialized bug of btb and jbtac write
|
| #
e76965b5 |
| 10-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: add debug info
ifu: fix pnpc vector in fetchPacket
|
| #
7995d245 |
| 09-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: fix btbData waymask assignment error
|
| #
f95e78ec |
| 09-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: add update logic of btb, jbtac and ghr
|
| #
627c0a19 |
| 09-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: split 8 btb targets into 8 ways in a SRAM
|
| #
2f99ffdd |
| 08-Jul-2020 |
GouLingrui <[email protected]> |
Merged
|
| #
96a51339 |
| 08-Jul-2020 |
GouLingrui <[email protected]> |
Try to merge
|
| #
0ba47cca |
| 08-Jul-2020 |
GouLingrui <[email protected]> |
Try to merge
|
| #
f5c046cd |
| 08-Jul-2020 |
zhanglinjuan <[email protected]> |
bpu: fix history shifting logic in Stage3
|
| #
028970c4 |
| 08-Jul-2020 |
zhanglinjuan <[email protected]> |
tage: add tage outer module
|