1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.utils._ 7import xiangshan.backend.ALUOpType 8import utils._ 9 10class TableAddr(val idxBits: Int, val banks: Int) extends XSBundle { 11 def tagBits = VAddrBits - idxBits - 2 12 13 val tag = UInt(tagBits.W) 14 val idx = UInt(idxBits.W) 15 val offset = UInt(2.W) 16 17 def fromUInt(x: UInt) = x.asTypeOf(UInt(VAddrBits.W)).asTypeOf(this) 18 def getTag(x: UInt) = fromUInt(x).tag 19 def getIdx(x: UInt) = fromUInt(x).idx 20 def getBank(x: UInt) = getIdx(x)(log2Up(banks) - 1, 0) 21 def getBankIdx(x: UInt) = getIdx(x)(idxBits - 1, log2Up(banks)) 22} 23 24class Stage1To2IO extends XSBundle { 25 val pc = Output(UInt(VAddrBits.W)) 26 val btb = new Bundle { 27 val hits = Output(UInt(FetchWidth.W)) 28 val targets = Output(Vec(FetchWidth, UInt(VAddrBits.W))) 29 } 30 val jbtac = new Bundle { 31 val hitIdx = Output(UInt(FetchWidth.W)) 32 val target = Output(UInt(VAddrBits.W)) 33 } 34 val tage = new Bundle { 35 val hits = Output(UInt(FetchWidth.W)) 36 val takens = Output(Vec(FetchWidth, Bool())) 37 } 38 val hist = Output(Vec(FetchWidth, UInt(HistoryLength.W))) 39 val btbPred = ValidIO(new BranchPrediction) 40} 41 42class BPUStage1 extends XSModule { 43 val io = IO(new Bundle() { 44 val in = new Bundle { val pc = Flipped(Decoupled(UInt(VAddrBits.W))) } 45 // from backend 46 val redirectInfo = Input(new RedirectInfo) 47 // from Stage3 48 val flush = Input(Bool()) 49 val s3RollBackHist = Input(UInt(HistoryLength.W)) 50 val s3Taken = Input(Bool()) 51 // to ifu, quick prediction result 52 val s1OutPred = ValidIO(new BranchPrediction) 53 // to Stage2 54 val out = Decoupled(new Stage1To2IO) 55 }) 56 57 // flush Stage1 when io.flush 58 val flushS1 = BoolStopWatch(io.flush, io.in.pc.fire(), startHighPriority = true) 59 60 // global history register 61 val ghr = RegInit(0.U(HistoryLength.W)) 62 // modify updateGhr and newGhr when updating ghr 63 val updateGhr = WireInit(false.B) 64 val newGhr = WireInit(0.U(HistoryLength.W)) 65 when (updateGhr) { ghr := newGhr } 66 // use hist as global history!!! 67 val hist = Mux(updateGhr, newGhr, ghr) 68 69 // Tage predictor 70 // val tage = Module(new FakeTAGE) 71 val tage = if(EnableBPD) Module(new Tage) else Module(new FakeTAGE) 72 tage.io.req.valid := io.in.pc.fire() 73 tage.io.req.bits.pc := io.in.pc.bits 74 tage.io.req.bits.hist := hist 75 tage.io.redirectInfo <> io.redirectInfo 76 io.out.bits.tage <> tage.io.out 77 io.s1OutPred.bits.tageMeta := tage.io.meta 78 79 // BTB 80 val btbAddr = new TableAddr(log2Up(BtbSets), BtbBanks) 81 val predictWidth = FetchWidth 82 def btbDataEntry() = new Bundle { 83 val valid = Bool() 84 val target = UInt(VAddrBits.W) 85 val pred = UInt(2.W) // 2-bit saturated counter as a quick predictor 86 val _type = UInt(2.W) 87 val offset = UInt(offsetBits().W) // Could be zero 88 89 def offsetBits() = log2Up(FetchWidth / predictWidth) 90 } 91 def btbMetaEntry() = new Bundle { 92 val valid = Bool() 93 // TODO: don't need full length of tag 94 val tag = UInt(btbAddr.tagBits.W) 95 } 96 97 val btbMeta = List.fill(BtbWays)(List.fill(BtbBanks)( 98 Module(new SRAMTemplate(btbMetaEntry(), set = BtbSets / BtbBanks, way = 1, shouldReset = true, holdRead = true)) 99 )) 100 val btbData = List.fill(BtbWays)(List.fill(BtbBanks)( 101 Module(new SRAMTemplate(btbDataEntry(), set = BtbSets / BtbBanks, way = predictWidth, shouldReset = true, holdRead = true)) 102 )) 103 104 // BTB read requests 105 // read addr comes from pc[6:2] 106 // read 4 ways in parallel 107 (0 until BtbWays).map( 108 w => (0 until BtbBanks).map( 109 b => { 110 btbMeta(w)(b).reset := reset.asBool 111 btbMeta(w)(b).io.r.req.valid := io.in.pc.fire() && b.U === btbAddr.getBank(io.in.pc.bits) 112 btbMeta(w)(b).io.r.req.bits.setIdx := btbAddr.getBankIdx(io.in.pc.bits) 113 btbData(w)(b).reset := reset.asBool 114 btbData(w)(b).io.r.req.valid := io.in.pc.fire() && b.U === btbAddr.getBank(io.in.pc.bits) 115 btbData(w)(b).io.r.req.bits.setIdx := btbAddr.getBankIdx(io.in.pc.bits) 116 } 117 ) 118 ) 119 120 // latch pc for 1 cycle latency when reading SRAM 121 val pcLatch = RegEnable(io.in.pc.bits, io.in.pc.fire()) 122 // Entries read from SRAM 123 val btbMetaRead = Wire(Vec(BtbWays, btbMetaEntry())) 124 val btbDataRead = Wire(Vec(BtbWays, Vec(predictWidth, btbDataEntry()))) 125 val btbReadFire = Wire(Vec(BtbWays, Vec(BtbBanks, Bool()))) 126 // 1/4 hit 127 val btbWayHits = Wire(Vec(BtbWays, Bool())) 128 129 // #(predictWidth) results 130 val btbTargets = Wire(Vec(predictWidth, UInt(VAddrBits.W))) 131 val btbTypes = Wire(Vec(predictWidth, UInt(2.W))) 132 // val btbPreds = Wire(Vec(FetchWidth, UInt(2.W))) 133 val btbCtrs = Wire(Vec(predictWidth, UInt(2.W))) 134 val btbTakens = Wire(Vec(predictWidth, Bool())) 135 val btbValids = Wire(Vec(predictWidth, Bool())) 136 137 val btbHitWay = Wire(UInt(log2Up(BtbWays).W)) 138 val btbHitBank = btbAddr.getBank(pcLatch) 139 140 btbMetaRead := DontCare 141 btbDataRead := DontCare 142 for (w <- 0 until BtbWays) { 143 for (b <- 0 until BtbBanks) { 144 when (b.U === btbHitBank) { 145 btbMetaRead(w) := btbMeta(w)(b).io.r.resp.data(0) 146 (0 until predictWidth).map(i => btbDataRead(w)(i) := btbData(w)(b).io.r.resp.data(i)) 147 } 148 } 149 } 150 151 btbWayHits := 0.U.asTypeOf(Vec(BtbWays, Bool())) 152 btbValids := 0.U.asTypeOf(Vec(predictWidth, Bool())) 153 btbTargets := DontCare 154 btbCtrs := DontCare 155 btbTakens := DontCare 156 btbTypes := DontCare 157 for (w <- 0 until BtbWays) { 158 for (b <- 0 until BtbBanks) { btbReadFire(w)(b) := btbMeta(w)(b).io.r.req.fire() && btbData(w)(b).io.r.req.fire() } 159 when (btbMetaRead(w).valid && btbMetaRead(w).tag === btbAddr.getTag(pcLatch)) { 160 // btbWayHits(w) := !flushS1 && RegNext(btbReadFire(w)(btbHitBank), init = false.B) 161 btbWayHits(w) := !io.flush && RegNext(btbReadFire(w)(btbHitBank), init = false.B) 162 for (i <- 0 until predictWidth) { 163 btbValids(i) := btbDataRead(w)(i).valid 164 btbTargets(i) := btbDataRead(w)(i).target 165 btbCtrs(i) := btbDataRead(w)(i).pred 166 btbTakens(i) := (btbDataRead(w)(i).pred)(1).asBool 167 btbTypes(i) := btbDataRead(w)(i)._type 168 } 169 } 170 } 171 172 val btbHit = btbWayHits.reduce(_|_) 173 btbHitWay := OHToUInt(HighestBit(btbWayHits.asUInt, BtbWays)) 174 175 // Priority mux which corresponds with inst orders 176 // BTB only produce one single prediction 177 val btbJumps = Wire(Vec(predictWidth, Bool())) 178 (0 until predictWidth).map(i => btbJumps(i) := btbValids(i) && (btbTypes(i) === BTBtype.J || btbTypes(i) === BTBtype.B && btbTakens(i))) 179 val btbTakenTarget = MuxCase(0.U, btbJumps zip btbTargets) 180 val btbTakenType = MuxCase(0.U, btbJumps zip btbTypes) 181 val btbTaken = btbJumps.reduce(_|_) 182 // Record which inst is predicted taken 183 val btbTakenIdx = MuxCase(0.U, btbJumps zip (0 until predictWidth).map(_.U)) 184 185 // JBTAC, divided into 8 banks, makes prediction for indirect jump except ret. 186 val jbtacAddr = new TableAddr(log2Up(JbtacSize), JbtacBanks) 187 def jbtacEntry() = new Bundle { 188 val valid = Bool() 189 // TODO: don't need full length of tag and target 190 val tag = UInt(jbtacAddr.tagBits.W) 191 val target = UInt(VAddrBits.W) 192 val offset = UInt(log2Up(FetchWidth).W) 193 } 194 195 val jbtac = List.fill(JbtacBanks)(Module(new SRAMTemplate(jbtacEntry(), set = JbtacSize / JbtacBanks, shouldReset = true, holdRead = true, singlePort = false))) 196 197 val jbtacRead = Wire(Vec(JbtacBanks, jbtacEntry())) 198 199 val jbtacFire = Reg(Vec(JbtacBanks, Bool())) 200 // Only read one bank 201 val histXORAddr = io.in.pc.bits ^ Cat(hist, 0.U(2.W))(VAddrBits - 1, 0) 202 val histXORAddrLatch = RegEnable(histXORAddr, io.in.pc.valid) 203 jbtacFire := 0.U.asTypeOf(Vec(JbtacBanks, Bool())) 204 (0 until JbtacBanks).map( 205 b => { 206 jbtac(b).reset := reset.asBool 207 jbtac(b).io.r.req.valid := io.in.pc.fire() && b.U === jbtacAddr.getBank(histXORAddr) 208 jbtac(b).io.r.req.bits.setIdx := jbtacAddr.getBankIdx(histXORAddr) 209 jbtacFire(b) := jbtac(b).io.r.req.fire() 210 jbtacRead(b) := jbtac(b).io.r.resp.data(0) 211 } 212 ) 213 214 val jbtacBank = jbtacAddr.getBank(histXORAddrLatch) 215 // val jbtacHit = jbtacRead(jbtacBank).valid && jbtacRead(jbtacBank).tag === jbtacAddr.getTag(pcLatch) && !flushS1 && jbtacFire(jbtacBank) 216 val jbtacHit = jbtacRead(jbtacBank).valid && jbtacRead(jbtacBank).tag === jbtacAddr.getTag(pcLatch) && !io.flush && jbtacFire(jbtacBank) 217 val jbtacHitIdx = jbtacRead(jbtacBank).offset 218 val jbtacTarget = jbtacRead(jbtacBank).target 219 220 // choose one way as victim way 221 val btbWayInvalids = Reverse(Cat(btbMetaRead.map(e => !e.valid)).asUInt) 222 val victim = Mux(btbHit, btbHitWay, Mux(btbWayInvalids.orR, OHToUInt(LowestBit(btbWayInvalids, BtbWays)), LFSR64()(log2Up(BtbWays) - 1, 0))) 223 224 // calculate global history of each instr 225 val firstHist = RegNext(hist) 226 val histShift = Wire(Vec(FetchWidth, UInt(log2Up(FetchWidth).W))) 227 val btbNotTakens = Wire(Vec(FetchWidth, Bool())) 228 (0 until FetchWidth).map(i => btbNotTakens(i) := btbValids(i) && btbTypes(i) === BTBtype.B && !btbCtrs(1)) 229 val shift = Wire(Vec(FetchWidth, Vec(FetchWidth, UInt(1.W)))) 230 (0 until FetchWidth).map(i => shift(i) := Mux(!btbNotTakens(i), 0.U, ~LowerMask(UIntToOH(i.U), FetchWidth)).asTypeOf(Vec(FetchWidth, UInt(1.W)))) 231 for (j <- 0 until FetchWidth) { 232 var tmp = 0.U 233 for (i <- 0 until FetchWidth) { 234 tmp = tmp + shift(i)(j) 235 } 236 histShift(j) := tmp 237 } 238 (0 until FetchWidth).map(i => io.s1OutPred.bits.hist(i) := firstHist << histShift(i)) 239 240 // update btb, jbtac, ghr 241 val r = io.redirectInfo.redirect 242 val updateFetchpc = r.pc - r.fetchIdx << 2.U 243 val updateMisPred = io.redirectInfo.misPred 244 val updateFetchIdx = r.fetchIdx 245 val updateVictimWay = r.btbVictimWay 246 val updateOldCtr = r.btbPredCtr 247 // 1. update btb 248 // 1.1 calculate new 2-bit saturated counter value 249 val newPredCtr = Mux(!r.btbHitWay, "b01".U, Mux(r.taken, Mux(updateOldCtr === "b11".U, "b11".U, updateOldCtr + 1.U), 250 Mux(updateOldCtr === "b00".U, "b00".U, updateOldCtr - 1.U))) 251 // 1.2 write btb 252 val updateBank = btbAddr.getBank(updateFetchpc) 253 val updateBankIdx = btbAddr.getBankIdx(updateFetchpc) 254 val updateWaymask = UIntToOH(updateFetchIdx) 255 val btbMetaWrite = Wire(btbMetaEntry()) 256 btbMetaWrite.valid := true.B 257 btbMetaWrite.tag := btbAddr.getTag(updateFetchpc) 258 val btbDataWrite = Wire(btbDataEntry()) 259 btbDataWrite.valid := true.B 260 btbDataWrite.target := r.brTarget 261 btbDataWrite.pred := newPredCtr 262 btbDataWrite._type := r._type 263 btbDataWrite.offset := DontCare 264 val btbWriteValid = io.redirectInfo.valid && (r._type === BTBtype.B || r._type === BTBtype.J) 265 266 for (w <- 0 until BtbWays) { 267 for (b <- 0 until BtbBanks) { 268 // println(s"${btbData(w)(b).io.w.req.bits.waymask.nonEmpty}") 269 when (b.U === updateBank && w.U === updateVictimWay) { 270 btbMeta(w)(b).io.w.req.valid := btbWriteValid 271 btbMeta(w)(b).io.w.req.bits.setIdx := updateBankIdx 272 btbMeta(w)(b).io.w.req.bits.data := btbMetaWrite 273 btbData(w)(b).io.w.req.valid := btbWriteValid 274 btbData(w)(b).io.w.req.bits.setIdx := updateBankIdx 275 btbData(w)(b).io.w.req.bits.waymask.map(_ := updateWaymask) 276 btbData(w)(b).io.w.req.bits.data := btbDataWrite 277 }.otherwise { 278 btbMeta(w)(b).io.w.req.valid := false.B 279 btbMeta(w)(b).io.w.req.bits.setIdx := DontCare 280 btbMeta(w)(b).io.w.req.bits.data := DontCare 281 btbData(w)(b).io.w.req.valid := false.B 282 btbData(w)(b).io.w.req.bits.setIdx := DontCare 283 btbData(w)(b).io.w.req.bits.waymask.map(_ := 0.U) 284 btbData(w)(b).io.w.req.bits.data := DontCare 285 } 286 } 287 } 288 289 // 2. update jbtac 290 val jbtacWrite = Wire(jbtacEntry()) 291 val updateHistXORAddr = updateFetchpc ^ Cat(r.hist, 0.U(2.W))(VAddrBits - 1, 0) 292 jbtacWrite.valid := true.B 293 jbtacWrite.tag := jbtacAddr.getTag(updateFetchpc) 294 jbtacWrite.target := r.target 295 jbtacWrite.offset := updateFetchIdx 296 for (b <- 0 until JbtacBanks) { 297 when (b.U === jbtacAddr.getBank(updateHistXORAddr)) { 298 jbtac(b).io.w.req.valid := io.redirectInfo.valid && updateMisPred && r._type === BTBtype.I 299 jbtac(b).io.w.req.bits.setIdx := jbtacAddr.getBankIdx(updateHistXORAddr) 300 jbtac(b).io.w.req.bits.data := jbtacWrite 301 }.otherwise { 302 jbtac(b).io.w.req.valid := false.B 303 jbtac(b).io.w.req.bits.setIdx := DontCare 304 jbtac(b).io.w.req.bits.data := DontCare 305 } 306 } 307 308 // 3. update ghr 309 updateGhr := io.s1OutPred.bits.redirect || io.flush 310 val brJumpIdx = Mux(!(btbHit && btbTaken), 0.U, UIntToOH(btbTakenIdx)) 311 val indirectIdx = Mux(!jbtacHit, 0.U, UIntToOH(jbtacHitIdx)) 312 //val newTaken = Mux(io.redirectInfo.flush(), !(r._type === BTBtype.B && !r.taken), ) 313 newGhr := Mux(io.redirectInfo.flush(), (r.hist << 1.U) | !(r._type === BTBtype.B && !r.taken), 314 Mux(io.flush, Mux(io.s3Taken, io.s3RollBackHist << 1.U | 1.U, io.s3RollBackHist), 315 Mux(io.s1OutPred.bits.redirect, PriorityMux(brJumpIdx | indirectIdx, io.s1OutPred.bits.hist) << 1.U | 1.U, 316 io.s1OutPred.bits.hist(0) << PopCount(btbNotTakens)))) 317 318 // redirect based on BTB and JBTAC 319 // io.out.valid := RegNext(io.in.pc.fire()) && !flushS1 320 io.out.valid := RegNext(io.in.pc.fire()) && !io.flush 321 322 io.s1OutPred.valid := io.out.valid 323 io.s1OutPred.bits.redirect := btbHit && btbTaken || jbtacHit 324 // io.s1OutPred.bits.instrValid := LowerMask(UIntToOH(btbTakenIdx), FetchWidth) & LowerMask(UIntToOH(jbtacHitIdx), FetchWidth) 325 io.s1OutPred.bits.instrValid := Mux(io.s1OutPred.bits.redirect, LowerMask(LowestBit(brJumpIdx | indirectIdx, FetchWidth), FetchWidth), Fill(FetchWidth, 1.U(1.W))).asTypeOf(Vec(FetchWidth, Bool())) 326 io.s1OutPred.bits.target := Mux(brJumpIdx === LowestBit(brJumpIdx | indirectIdx, FetchWidth), btbTakenTarget, jbtacTarget) 327 io.s1OutPred.bits.btbVictimWay := victim 328 io.s1OutPred.bits.predCtr := btbCtrs 329 io.s1OutPred.bits.btbHitWay := btbHit 330 io.s1OutPred.bits.rasSp := DontCare 331 io.s1OutPred.bits.rasTopCtr := DontCare 332 333 io.out.bits.pc := pcLatch 334 io.out.bits.btb.hits := btbValids.asUInt 335 (0 until FetchWidth).map(i => io.out.bits.btb.targets(i) := btbTargets(i)) 336 io.out.bits.jbtac.hitIdx := UIntToOH(jbtacHitIdx) 337 io.out.bits.jbtac.target := jbtacTarget 338 // TODO: we don't need this repeatedly! 339 io.out.bits.hist := io.s1OutPred.bits.hist 340 io.out.bits.btbPred := io.s1OutPred 341 342 io.in.pc.ready := true.B 343 344 // debug info 345 XSDebug(true.B, "[BPUS1]in:(%d %d) pc=%x ghr=%b\n", io.in.pc.valid, io.in.pc.ready, io.in.pc.bits, hist) 346 XSDebug(true.B, "[BPUS1]outPred:(%d) redirect=%d instrValid=%b tgt=%x\n", 347 io.s1OutPred.valid, io.s1OutPred.bits.redirect, io.s1OutPred.bits.instrValid.asUInt, io.s1OutPred.bits.target) 348 XSDebug(io.flush && io.redirectInfo.flush(), 349 "[BPUS1]flush from backend: pc=%x tgt=%x brTgt=%x _type=%b taken=%d oldHist=%b fetchIdx=%d isExcpt=%d\n", 350 r.pc, r.target, r.brTarget, r._type, r.taken, r.hist, r.fetchIdx, r.isException) 351 XSDebug(io.flush && !io.redirectInfo.flush(), 352 "[BPUS1]flush from Stage3: s3Taken=%d s3RollBackHist=%b\n", io.s3Taken, io.s3RollBackHist) 353 354} 355 356class Stage2To3IO extends Stage1To2IO { 357} 358 359class BPUStage2 extends XSModule { 360 val io = IO(new Bundle() { 361 // flush from Stage3 362 val flush = Input(Bool()) 363 val in = Flipped(Decoupled(new Stage1To2IO)) 364 val out = Decoupled(new Stage2To3IO) 365 }) 366 367 // flush Stage2 when Stage3 or banckend redirects 368 val flushS2 = BoolStopWatch(io.flush, io.in.fire(), startHighPriority = true) 369 io.out.valid := !io.flush && !flushS2 && RegNext(io.in.fire()) 370 io.in.ready := !io.out.valid || io.out.fire() 371 372 // do nothing 373 io.out.bits := RegEnable(io.in.bits, io.in.fire()) 374 375 // debug info 376 XSDebug(true.B, "[BPUS2]in:(%d %d) pc=%x out:(%d %d) pc=%x\n", 377 io.in.valid, io.in.ready, io.in.bits.pc, io.out.valid, io.out.ready, io.out.bits.pc) 378 XSDebug(io.flush, "[BPUS2]flush!!!\n") 379} 380 381class BPUStage3 extends XSModule { 382 val io = IO(new Bundle() { 383 val flush = Input(Bool()) 384 val in = Flipped(Decoupled(new Stage2To3IO)) 385 val out = ValidIO(new BranchPrediction) 386 // from icache 387 val predecode = Flipped(ValidIO(new Predecode)) 388 // from backend 389 val redirectInfo = Input(new RedirectInfo) 390 // to Stage1 and Stage2 391 val flushBPU = Output(Bool()) 392 // to Stage1, restore ghr in stage1 when flushBPU is valid 393 val s1RollBackHist = Output(UInt(HistoryLength.W)) 394 val s3Taken = Output(Bool()) 395 }) 396 397 val flushS3 = BoolStopWatch(io.flush, io.in.fire(), startHighPriority = true) 398 val inLatch = RegInit(0.U.asTypeOf(io.in.bits)) 399 val validLatch = RegInit(false.B) 400 when (io.in.fire()) { inLatch := io.in.bits } 401 when (io.in.fire()) { 402 validLatch := !io.flush 403 }.elsewhen (io.out.valid) { 404 validLatch := false.B 405 } 406 io.out.valid := validLatch && io.predecode.valid && !flushS3 407 io.in.ready := !validLatch || io.out.valid 408 409 // RAS 410 // TODO: split retAddr and ctr 411 def rasEntry() = new Bundle { 412 val retAddr = UInt(VAddrBits.W) 413 val ctr = UInt(8.W) // layer of nested call functions 414 } 415 val ras = RegInit(VecInit(Seq.fill(RasSize)(0.U.asTypeOf(rasEntry())))) 416 val sp = Counter(RasSize) 417 val rasTop = ras(sp.value) 418 val rasTopAddr = rasTop.retAddr 419 420 // get the first taken branch/jal/call/jalr/ret in a fetch line 421 // brTakenIdx/jalIdx/callIdx/jalrIdx/retIdx/jmpIdx is one-hot encoded. 422 // brNotTakenIdx indicates all the not-taken branches before the first jump instruction. 423 val brIdx = inLatch.btb.hits & Reverse(Cat(io.predecode.bits.fuOpTypes.map { t => ALUOpType.isBranch(t) }).asUInt) & io.predecode.bits.mask 424 val brTakenIdx = LowestBit(brIdx & inLatch.tage.takens.asUInt, FetchWidth) 425 val jalIdx = LowestBit(inLatch.btb.hits & Reverse(Cat(io.predecode.bits.fuOpTypes.map { t => t === ALUOpType.jal }).asUInt) & io.predecode.bits.mask, FetchWidth) 426 val callIdx = LowestBit(inLatch.btb.hits & io.predecode.bits.mask & Reverse(Cat(io.predecode.bits.fuOpTypes.map { t => t === ALUOpType.call }).asUInt), FetchWidth) 427 val jalrIdx = LowestBit(inLatch.jbtac.hitIdx & io.predecode.bits.mask & Reverse(Cat(io.predecode.bits.fuOpTypes.map { t => t === ALUOpType.jalr }).asUInt), FetchWidth) 428 val retIdx = LowestBit(io.predecode.bits.mask & Reverse(Cat(io.predecode.bits.fuOpTypes.map { t => t === ALUOpType.ret }).asUInt), FetchWidth) 429 430 val jmpIdx = LowestBit(brTakenIdx | jalIdx | callIdx | jalrIdx | retIdx, FetchWidth) 431 val brNotTakenIdx = brIdx & ~inLatch.tage.takens.asUInt & LowerMask(jmpIdx, FetchWidth) & io.predecode.bits.mask 432 433 io.out.bits.redirect := jmpIdx.orR.asBool 434 io.out.bits.target := Mux(jmpIdx === retIdx, rasTopAddr, 435 Mux(jmpIdx === jalrIdx, inLatch.jbtac.target, 436 Mux(jmpIdx === 0.U, inLatch.pc + 32.U, // TODO: RVC 437 PriorityMux(jmpIdx, inLatch.btb.targets)))) 438 io.out.bits.instrValid := Mux(jmpIdx.orR, LowerMask(jmpIdx, FetchWidth), Fill(FetchWidth, 1.U(1.W))).asTypeOf(Vec(FetchWidth, Bool())) 439 io.out.bits.btbVictimWay := inLatch.btbPred.bits.btbVictimWay 440 io.out.bits.predCtr := inLatch.btbPred.bits.predCtr 441 io.out.bits.btbHitWay := inLatch.btbPred.bits.btbHitWay 442 io.out.bits.tageMeta := inLatch.btbPred.bits.tageMeta 443 //io.out.bits._type := Mux(jmpIdx === retIdx, BTBtype.R, 444 // Mux(jmpIdx === jalrIdx, BTBtype.I, 445 // Mux(jmpIdx === brTakenIdx, BTBtype.B, BTBtype.J))) 446 val firstHist = inLatch.btbPred.bits.hist(0) 447 // there may be several notTaken branches before the first jump instruction, 448 // so we need to calculate how many zeroes should each instruction shift in its global history. 449 // each history is exclusive of instruction's own jump direction. 450 val histShift = Wire(Vec(FetchWidth, UInt(log2Up(FetchWidth).W))) 451 val shift = Wire(Vec(FetchWidth, Vec(FetchWidth, UInt(1.W)))) 452 (0 until FetchWidth).map(i => shift(i) := Mux(!brNotTakenIdx(i), 0.U, ~LowerMask(UIntToOH(i.U), FetchWidth)).asTypeOf(Vec(FetchWidth, UInt(1.W)))) 453 for (j <- 0 until FetchWidth) { 454 var tmp = 0.U 455 for (i <- 0 until FetchWidth) { 456 tmp = tmp + shift(i)(j) 457 } 458 histShift(j) := tmp 459 } 460 (0 until FetchWidth).map(i => io.out.bits.hist(i) := firstHist << histShift(i)) 461 // save ras checkpoint info 462 io.out.bits.rasSp := sp.value 463 io.out.bits.rasTopCtr := rasTop.ctr 464 465 // flush BPU and redirect when target differs from the target predicted in Stage1 466 io.out.bits.redirect := inLatch.btbPred.bits.redirect ^ jmpIdx.orR.asBool || 467 inLatch.btbPred.bits.redirect && jmpIdx.orR.asBool && io.out.bits.target =/= inLatch.btbPred.bits.target 468 io.flushBPU := io.out.bits.redirect && io.out.valid 469 470 // speculative update RAS 471 val rasWrite = WireInit(0.U.asTypeOf(rasEntry())) 472 rasWrite.retAddr := inLatch.pc + OHToUInt(callIdx) << 2.U + 4.U 473 val allocNewEntry = rasWrite.retAddr =/= rasTopAddr 474 rasWrite.ctr := Mux(allocNewEntry, 1.U, rasTop.ctr + 1.U) 475 when (io.out.valid) { 476 when (jmpIdx === callIdx) { 477 ras(Mux(allocNewEntry, sp.value + 1.U, sp.value)) := rasWrite 478 when (allocNewEntry) { sp.value := sp.value + 1.U } 479 }.elsewhen (jmpIdx === retIdx) { 480 when (rasTop.ctr === 1.U) { 481 sp.value := Mux(sp.value === 0.U, 0.U, sp.value - 1.U) 482 }.otherwise { 483 ras(sp.value) := Cat(rasTop.ctr - 1.U, rasTopAddr).asTypeOf(rasEntry()) 484 } 485 } 486 } 487 // use checkpoint to recover RAS 488 val recoverSp = io.redirectInfo.redirect.rasSp 489 val recoverCtr = io.redirectInfo.redirect.rasTopCtr 490 when (io.redirectInfo.valid && io.redirectInfo.misPred) { 491 sp.value := recoverSp 492 ras(recoverSp) := Cat(recoverCtr, ras(recoverSp).retAddr).asTypeOf(rasEntry()) 493 } 494 495 // roll back global history in S1 if S3 redirects 496 io.s1RollBackHist := Mux(io.s3Taken, PriorityMux(jmpIdx, io.out.bits.hist), io.out.bits.hist(0) << PopCount(brIdx & ~inLatch.tage.takens.asUInt)) 497 // whether Stage3 has a taken jump 498 io.s3Taken := jmpIdx.orR.asBool 499 500 // debug info 501 XSDebug(io.in.fire(), "[BPUS3]in:(%d %d) pc=%x\n", io.in.valid, io.in.ready, io.in.bits.pc) 502 XSDebug(io.out.valid, "[BPUS3]out:%d pc=%x redirect=%d predcdMask=%b instrValid=%b tgt=%x\n", 503 io.out.valid, inLatch.pc, io.out.bits.redirect, io.predecode.bits.mask, io.out.bits.instrValid.asUInt, io.out.bits.target) 504 XSDebug(true.B, "[BPUS3]flushS3=%d\n", flushS3) 505 XSDebug(true.B, "[BPUS3]validLatch=%d predecode.valid=%d\n", validLatch, io.predecode.valid) 506 XSDebug(true.B, "[BPUS3]brIdx=%b brTakenIdx=%b brNTakenIdx=%b jalIdx=%d jalrIdx=%d callIdx=%d retIdx=%b\n", 507 brIdx, brTakenIdx, brNotTakenIdx, jalIdx, jalrIdx, callIdx, retIdx) 508} 509 510class BPU extends XSModule { 511 val io = IO(new Bundle() { 512 // from backend 513 // flush pipeline if misPred and update bpu based on redirect signals from brq 514 val redirectInfo = Input(new RedirectInfo) 515 516 val in = new Bundle { val pc = Flipped(Valid(UInt(VAddrBits.W))) } 517 518 val btbOut = ValidIO(new BranchPrediction) 519 val tageOut = ValidIO(new BranchPrediction) 520 521 // predecode info from icache 522 // TODO: simplify this after implement predecode unit 523 val predecode = Flipped(ValidIO(new Predecode)) 524 }) 525 526 val s1 = Module(new BPUStage1) 527 val s2 = Module(new BPUStage2) 528 val s3 = Module(new BPUStage3) 529 530 s1.io.redirectInfo <> io.redirectInfo 531 s1.io.flush := s3.io.flushBPU || io.redirectInfo.flush() 532 s1.io.in.pc.valid := io.in.pc.valid 533 s1.io.in.pc.bits <> io.in.pc.bits 534 io.btbOut <> s1.io.s1OutPred 535 s1.io.s3RollBackHist := s3.io.s1RollBackHist 536 s1.io.s3Taken := s3.io.s3Taken 537 538 s1.io.out <> s2.io.in 539 s2.io.flush := s3.io.flushBPU || io.redirectInfo.flush() 540 541 s2.io.out <> s3.io.in 542 s3.io.flush := io.redirectInfo.flush() 543 s3.io.predecode <> io.predecode 544 io.tageOut <> s3.io.out 545 s3.io.redirectInfo <> io.redirectInfo 546}