xref: /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala (revision 7995d2453b68c9aab514323329d28948bac2eb77)
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.utils._
7import xiangshan.backend.ALUOpType
8import utils._
9
10class TableAddr(val idxBits: Int, val banks: Int) extends XSBundle {
11  def tagBits = VAddrBits - idxBits - 2
12
13  val tag = UInt(tagBits.W)
14  val idx = UInt(idxBits.W)
15  val offset = UInt(2.W)
16
17  def fromUInt(x: UInt) = x.asTypeOf(UInt(VAddrBits.W)).asTypeOf(this)
18  def getTag(x: UInt) = fromUInt(x).tag
19  def getIdx(x: UInt) = fromUInt(x).idx
20  def getBank(x: UInt) = getIdx(x)(log2Up(banks) - 1, 0)
21  def getBankIdx(x: UInt) = getIdx(x)(idxBits - 1, log2Up(banks))
22}
23
24class Stage1To2IO extends XSBundle {
25  val pc = Output(UInt(VAddrBits.W))
26  val btb = new Bundle {
27    val hits = Output(UInt(FetchWidth.W))
28    val targets = Output(Vec(FetchWidth, UInt(VAddrBits.W)))
29  }
30  val jbtac = new Bundle {
31    val hitIdx = Output(UInt(FetchWidth.W))
32    val target = Output(UInt(VAddrBits.W))
33  }
34  val tage = new Bundle {
35    val hits = Output(UInt(FetchWidth.W))
36    val takens = Output(Vec(FetchWidth, Bool()))
37  }
38  val hist = Output(Vec(FetchWidth, UInt(HistoryLength.W)))
39  val btbPred = ValidIO(new BranchPrediction)
40}
41
42class BPUStage1 extends XSModule {
43  val io = IO(new Bundle() {
44    val in = new Bundle { val pc = Flipped(Decoupled(UInt(VAddrBits.W))) }
45    // from backend
46    val redirectInfo = Flipped(new RedirectInfo)
47    // from Stage3
48    val flush = Input(Bool())
49    val s3RollBackHist = Input(UInt(HistoryLength.W))
50    val s3Taken = Input(Bool())
51    // to ifu, quick prediction result
52    val s1OutPred = ValidIO(new BranchPrediction)
53    // to Stage2
54    val out = Decoupled(new Stage1To2IO)
55  })
56
57  // flush Stage1 when io.flush
58  val flushS1 = BoolStopWatch(io.flush, io.in.pc.fire(), startHighPriority = true)
59
60  // global history register
61  val ghr = RegInit(0.U(HistoryLength.W))
62  // modify updateGhr and newGhr when updating ghr
63  val updateGhr = WireInit(false.B)
64  val newGhr = WireInit(0.U(HistoryLength.W))
65  when (updateGhr) { ghr := newGhr }
66  // use hist as global history!!!
67  val hist = Mux(updateGhr, newGhr, ghr)
68
69  // Tage predictor
70  val tage = Module(new Tage)
71  tage.io.req.valid := io.in.pc.fire()
72  tage.io.req.bits.pc := io.in.pc.bits
73  tage.io.req.bits.hist := hist
74  tage.io.redirectInfo <> io.redirectInfo
75  io.out.bits.tage <> tage.io.out
76  io.s1OutPred.bits.tageMeta := tage.io.meta
77
78  // BTB
79  val btbAddr = new TableAddr(log2Up(BtbSets), BtbBanks)
80  val predictWidth = FetchWidth
81  def btbDataEntry() = new Bundle {
82    val valid = Bool()
83    val target = UInt(VAddrBits.W)
84    val pred = UInt(2.W) // 2-bit saturated counter as a quick predictor
85    val _type = UInt(2.W)
86    val offset = UInt(offsetBits().W) // Could be zero
87
88    def offsetBits() = log2Up(FetchWidth / predictWidth)
89  }
90  def btbMetaEntry() = new Bundle {
91    val valid = Bool()
92    // TODO: don't need full length of tag
93    val tag = UInt(btbAddr.tagBits.W)
94  }
95
96  val btbMeta = List.fill(BtbWays)(List.fill(BtbBanks)(
97    Module(new SRAMTemplate(btbMetaEntry(), set = BtbSets / BtbBanks, way = 1, shouldReset = true, holdRead = true))
98  ))
99  val btbData = List.fill(BtbWays)(List.fill(BtbBanks)(
100    Module(new SRAMTemplate(btbDataEntry(), set = BtbSets / BtbBanks, way = predictWidth, shouldReset = true, holdRead = true))
101  ))
102
103  // BTB read requests
104  // read addr comes from pc[6:2]
105  // read 4 ways in parallel
106  (0 until BtbWays).map(
107    w => (0 until BtbBanks).map(
108      b => {
109        btbMeta(w)(b).reset := reset.asBool
110        btbMeta(w)(b).io.r.req.valid := io.in.pc.fire() && b.U === btbAddr.getBank(io.in.pc.bits)
111        btbMeta(w)(b).io.r.req.bits.setIdx := btbAddr.getBankIdx(io.in.pc.bits)
112        btbData(w)(b).reset := reset.asBool
113        btbData(w)(b).io.r.req.valid := io.in.pc.fire() && b.U === btbAddr.getBank(io.in.pc.bits)
114        btbData(w)(b).io.r.req.bits.setIdx := btbAddr.getBankIdx(io.in.pc.bits)
115      }
116    )
117  )
118
119  // latch pc for 1 cycle latency when reading SRAM
120  val pcLatch = RegEnable(io.in.pc.bits, io.in.pc.fire())
121  // Entries read from SRAM
122  val btbMetaRead = Wire(Vec(BtbWays, btbMetaEntry()))
123  val btbDataRead = Wire(Vec(BtbWays, Vec(predictWidth, btbDataEntry())))
124  val btbReadFire = Wire(Vec(BtbWays, Vec(BtbBanks, Bool())))
125  // 1/4 hit
126  val btbWayHits = Wire(Vec(BtbWays, Bool()))
127
128  // #(predictWidth) results
129  val btbTargets = Wire(Vec(predictWidth, UInt(VAddrBits.W)))
130  val btbTypes = Wire(Vec(predictWidth, UInt(2.W)))
131  // val btbPreds = Wire(Vec(FetchWidth, UInt(2.W)))
132  val btbCtrs = Wire(Vec(predictWidth, UInt(2.W)))
133  val btbTakens = Wire(Vec(predictWidth, Bool()))
134  val btbValids = Wire(Vec(predictWidth, Bool()))
135
136  val btbHitWay = Wire(UInt(log2Up(BtbWays).W))
137  val btbHitBank = btbAddr.getBank(pcLatch)
138
139  btbMetaRead := DontCare
140  btbDataRead := DontCare
141  for (w <- 0 until BtbWays) {
142    for (b <- 0 until BtbBanks) {
143      when (b.U === btbHitBank) {
144        btbMetaRead(w) := btbMeta(w)(b).io.r.resp.data(0)
145        (0 until predictWidth).map(i => btbDataRead(w)(i) := btbData(w)(b).io.r.resp.data(i))
146      }
147    }
148  }
149
150  btbWayHits := 0.U.asTypeOf(Vec(BtbWays, Bool()))
151  btbValids := 0.U.asTypeOf(Vec(predictWidth, Bool()))
152  btbTargets := DontCare
153  btbCtrs := DontCare
154  btbTakens := DontCare
155  btbTypes := DontCare
156  for (w <- 0 until BtbWays) {
157    for (b <- 0 until BtbBanks) { btbReadFire(w)(b) := btbMeta(w)(b).io.r.req.fire() && btbData(w)(b).io.r.req.fire() }
158    when (btbMetaRead(w).valid && btbMetaRead(w).tag === btbAddr.getTag(pcLatch)) {
159      btbWayHits(w) := !flushS1 && RegNext(btbReadFire(w)(btbHitBank), init = false.B)
160      for (i <- 0 until predictWidth) {
161        btbValids(i) := btbDataRead(w)(i).valid
162        btbTargets(i) := btbDataRead(w)(i).target
163        btbCtrs(i) := btbDataRead(w)(i).pred
164        btbTakens(i) := (btbDataRead(w)(i).pred)(1).asBool
165        btbTypes(i) := btbDataRead(w)(i)._type
166      }
167    }
168  }
169
170  val btbHit = btbWayHits.reduce(_|_)
171  btbHitWay := OHToUInt(HighestBit(btbWayHits.asUInt, BtbWays))
172
173  // Priority mux which corresponds with inst orders
174  // BTB only produce one single prediction
175  val btbJumps = Wire(Vec(predictWidth, Bool()))
176  (0 until predictWidth).map(i => btbJumps(i) := btbValids(i) && (btbTypes(i) === BTBtype.J || btbTypes(i) === BTBtype.B && btbTakens(i)))
177  val btbTakenTarget = MuxCase(0.U, btbJumps zip btbTargets)
178  val btbTakenType   = MuxCase(0.U, btbJumps zip btbTypes)
179  val btbTaken       = btbJumps.reduce(_|_)
180  // Record which inst is predicted taken
181  val btbTakenIdx = MuxCase(0.U, btbJumps zip (0 until predictWidth).map(_.U))
182
183  // JBTAC, divided into 8 banks, makes prediction for indirect jump except ret.
184  val jbtacAddr = new TableAddr(log2Up(JbtacSize), JbtacBanks)
185  def jbtacEntry() = new Bundle {
186    val valid = Bool()
187    // TODO: don't need full length of tag and target
188    val tag = UInt(jbtacAddr.tagBits.W)
189    val target = UInt(VAddrBits.W)
190    val offset = UInt(log2Up(FetchWidth).W)
191  }
192
193  val jbtac = List.fill(JbtacBanks)(Module(new SRAMTemplate(jbtacEntry(), set = JbtacSize / JbtacBanks, shouldReset = true, holdRead = true, singlePort = false)))
194
195  val jbtacRead = Wire(Vec(JbtacBanks, jbtacEntry()))
196
197  val jbtacFire = Reg(Vec(JbtacBanks, Bool()))
198  // Only read one bank
199  val histXORAddr = io.in.pc.bits ^ Cat(hist, 0.U(2.W))(VAddrBits - 1, 0)
200  val histXORAddrLatch = RegEnable(histXORAddr, io.in.pc.valid)
201  jbtacFire := 0.U.asTypeOf(Vec(JbtacBanks, Bool()))
202  (0 until JbtacBanks).map(
203    b => {
204      jbtac(b).reset := reset.asBool
205      jbtac(b).io.r.req.valid := io.in.pc.fire() && b.U === jbtacAddr.getBank(histXORAddr)
206      jbtac(b).io.r.req.bits.setIdx := jbtacAddr.getBankIdx(histXORAddr)
207      jbtacFire(b) := jbtac(b).io.r.req.fire()
208      jbtacRead(b) := jbtac(b).io.r.resp.data(0)
209    }
210  )
211
212  val jbtacBank = jbtacAddr.getBank(histXORAddrLatch)
213  val jbtacHit = jbtacRead(jbtacBank).valid && jbtacRead(jbtacBank).tag === jbtacAddr.getTag(pcLatch) && !flushS1 && jbtacFire(jbtacBank)
214  val jbtacHitIdx = jbtacRead(jbtacBank).offset
215  val jbtacTarget = jbtacRead(jbtacBank).target
216
217  // choose one way as victim way
218  val btbWayInvalids = Cat(btbMetaRead.map(e => !e.valid)).asUInt
219  val victim = Mux(btbHit, btbHitWay, Mux(btbWayInvalids.orR, OHToUInt(LowestBit(btbWayInvalids, BtbWays)), LFSR64()(log2Up(BtbWays) - 1, 0)))
220
221  // calculate global history of each instr
222  val firstHist = RegNext(hist)
223  val histShift = Wire(Vec(FetchWidth, UInt(log2Up(FetchWidth).W)))
224  val btbNotTakens = Wire(Vec(FetchWidth, Bool()))
225  (0 until FetchWidth).map(i => btbNotTakens(i) := btbValids(i) && btbTypes(i) === BTBtype.B && !btbCtrs(1))
226  val shift = Wire(Vec(FetchWidth, Vec(FetchWidth, UInt(1.W))))
227  (0 until FetchWidth).map(i => shift(i) := Mux(!btbNotTakens(i), 0.U, ~LowerMask(UIntToOH(i.U), FetchWidth)).asTypeOf(Vec(FetchWidth, UInt(1.W))))
228  for (j <- 0 until FetchWidth) {
229    var tmp = 0.U
230    for (i <- 0 until FetchWidth) {
231      tmp = tmp + shift(i)(j)
232    }
233    histShift(j) := tmp
234  }
235  (0 until FetchWidth).map(i => io.s1OutPred.bits.hist(i) := firstHist << histShift(i))
236
237  // update btb, jbtac, ghr
238  val r = io.redirectInfo.redirect
239  val updateFetchpc = r.pc - r.fetchIdx << 2.U
240  val updateMisPred = io.redirectInfo.misPred
241  val updateFetchIdx = r.fetchIdx
242  val updateVictimWay = r.btbVictimWay
243  val updateOldCtr = r.btbPredCtr
244  // 1. update btb
245  // 1.1 calculate new 2-bit saturated counter value
246  val newPredCtr = Mux(!r.btbHitWay, "b01".U, Mux(r.taken, Mux(updateOldCtr === "b11".U, "b11".U, updateOldCtr + 1.U),
247                                                           Mux(updateOldCtr === "b00".U, "b00".U, updateOldCtr - 1.U)))
248  // 1.2 write btb
249  val updateBank = btbAddr.getBank(updateFetchpc)
250  val updateBankIdx = btbAddr.getBankIdx(updateFetchpc)
251  val updateWaymask = UIntToOH(updateFetchIdx)
252  val btbMetaWrite = Wire(btbMetaEntry())
253  btbMetaWrite.valid := true.B
254  btbMetaWrite.tag := btbAddr.getTag(updateFetchpc)
255  val btbDataWrite = Wire(btbDataEntry())
256  btbDataWrite.valid := true.B
257  btbDataWrite.target := r.brTarget
258  btbDataWrite.pred := newPredCtr
259  btbDataWrite._type := r._type
260  btbDataWrite.offset := DontCare
261  val btbWriteValid = io.redirectInfo.valid && (r._type === BTBtype.B || r._type === BTBtype.J)
262
263  for (w <- 0 until BtbWays) {
264    for (b <- 0 until BtbBanks) {
265      when (b.U === updateBank && w.U === updateVictimWay) {
266        btbMeta(w)(b).io.w.req.valid := btbWriteValid
267        btbMeta(w)(b).io.w.req.bits.setIdx := updateBankIdx
268        btbMeta(w)(b).io.w.req.bits.data := btbMetaWrite
269        btbData(w)(b).io.w.req.valid := btbWriteValid
270        btbData(w)(b).io.w.req.bits.setIdx := updateBankIdx
271        btbData(w)(b).io.w.req.bits.waymask.map(_ := updateWaymask)
272        btbData(w)(b).io.w.req.bits.data := btbDataWrite
273      }.otherwise {
274        btbMeta(w)(b).io.w.req.valid := false.B
275        btbData(w)(b).io.w.req.valid := false.B
276      }
277    }
278  }
279
280  // 2. update jbtac
281  val jbtacWrite = Wire(jbtacEntry())
282  val updateHistXORAddr = updateFetchpc ^ Cat(r.hist, 0.U(2.W))(VAddrBits - 1, 0)
283  jbtacWrite.valid := true.B
284  jbtacWrite.tag := jbtacAddr.getTag(updateFetchpc)
285  jbtacWrite.target := r.target
286  jbtacWrite.offset := updateFetchIdx
287  for (b <- 0 until JbtacBanks) {
288    when (b.U === jbtacAddr.getBank(updateHistXORAddr)) {
289      jbtac(b).io.w.req.valid := io.redirectInfo.valid && updateMisPred && r._type === BTBtype.I
290      jbtac(b).io.w.req.bits.setIdx := jbtacAddr.getBankIdx(updateHistXORAddr)
291      jbtac(b).io.w.req.bits.data := jbtacWrite
292    }
293  }
294
295  // 3. update ghr
296  updateGhr := io.s1OutPred.bits.redirect || io.flush
297  val brJumpIdx = Mux(!(btbHit && btbTaken), 0.U, UIntToOH(btbTakenIdx))
298  val indirectIdx = Mux(!jbtacHit, 0.U, UIntToOH(jbtacHitIdx))
299  //val newTaken = Mux(io.redirectInfo.flush(), !(r._type === BTBtype.B && !r.taken), )
300  newGhr := Mux(io.redirectInfo.flush(),    (r.hist << 1.U) | !(r._type === BTBtype.B && !r.taken),
301            Mux(io.flush,                   Mux(io.s3Taken, io.s3RollBackHist << 1.U | 1.U, io.s3RollBackHist),
302            Mux(io.s1OutPred.bits.redirect, PriorityMux(brJumpIdx | indirectIdx, io.s1OutPred.bits.hist) << 1.U | 1.U,
303                                            io.s1OutPred.bits.hist(0) << PopCount(btbNotTakens))))
304
305  // redirect based on BTB and JBTAC
306  io.out.valid := RegNext(io.in.pc.fire()) && !flushS1
307
308  io.s1OutPred.valid := io.out.valid
309  io.s1OutPred.bits.redirect := btbHit && btbTaken || jbtacHit
310  // io.s1OutPred.bits.instrValid := LowerMask(UIntToOH(btbTakenIdx), FetchWidth) & LowerMask(UIntToOH(jbtacHitIdx), FetchWidth)
311  io.s1OutPred.bits.instrValid := Mux(io.s1OutPred.bits.redirect, LowerMask(LowestBit(brJumpIdx | indirectIdx, FetchWidth), FetchWidth), Fill(FetchWidth, 1.U(1.W))).asTypeOf(Vec(FetchWidth, Bool()))
312  io.s1OutPred.bits.target := Mux(brJumpIdx === LowestBit(brJumpIdx | indirectIdx, FetchWidth), btbTakenTarget, jbtacTarget)
313  io.s1OutPred.bits.btbVictimWay := victim
314  io.s1OutPred.bits.predCtr := btbCtrs
315  io.s1OutPred.bits.btbHitWay := btbHit
316  io.s1OutPred.bits.rasSp := DontCare
317  io.s1OutPred.bits.rasTopCtr := DontCare
318
319  io.out.bits.pc := pcLatch
320  io.out.bits.btb.hits := btbValids.asUInt
321  (0 until FetchWidth).map(i => io.out.bits.btb.targets(i) := btbTargets(i))
322  io.out.bits.jbtac.hitIdx := UIntToOH(jbtacHitIdx)
323  io.out.bits.jbtac.target := jbtacTarget
324  // TODO: we don't need this repeatedly!
325  io.out.bits.hist := io.s1OutPred.bits.hist
326  io.out.bits.btbPred := io.s1OutPred
327
328  io.in.pc.ready := true.B
329
330}
331
332class Stage2To3IO extends Stage1To2IO {
333}
334
335class BPUStage2 extends XSModule {
336  val io = IO(new Bundle() {
337    // flush from Stage3
338    val flush = Input(Bool())
339    val in = Flipped(Decoupled(new Stage1To2IO))
340    val out = Decoupled(new Stage2To3IO)
341  })
342
343  // flush Stage2 when Stage3 or banckend redirects
344  val flushS2 = BoolStopWatch(io.flush, io.in.fire(), startHighPriority = true)
345  io.out.valid := !flushS2 && RegNext(io.in.fire())
346  io.in.ready := !io.out.valid || io.out.fire()
347
348  // do nothing
349  io.out.bits := RegEnable(io.in.bits, io.in.fire())
350}
351
352class BPUStage3 extends XSModule {
353  val io = IO(new Bundle() {
354    val flush = Input(Bool())
355    val in = Flipped(Decoupled(new Stage2To3IO))
356    val out = ValidIO(new BranchPrediction)
357    // from icache
358    val predecode = Flipped(ValidIO(new Predecode))
359    // from backend
360    val redirectInfo = Flipped(new RedirectInfo)
361    // to Stage1 and Stage2
362    val flushBPU = Output(Bool())
363    // to Stage1, restore ghr in stage1 when flushBPU is valid
364    val s1RollBackHist = Output(UInt(HistoryLength.W))
365    val s3Taken = Output(Bool())
366  })
367
368  val flushS3 = BoolStopWatch(io.flush, io.in.fire(), startHighPriority = true)
369  val inLatch = RegInit(0.U.asTypeOf(io.in.bits))
370  val validLatch = RegInit(false.B)
371  when (io.in.fire()) { inLatch := io.in.bits }
372  when (io.in.fire()) {
373    validLatch := !io.flush
374  }.elsewhen (io.out.valid) {
375    validLatch := false.B
376  }
377  io.out.valid := validLatch && io.predecode.valid && !flushS3
378  io.in.ready := !validLatch || io.out.valid
379
380  // RAS
381  // TODO: split retAddr and ctr
382  def rasEntry() = new Bundle {
383    val retAddr = UInt(VAddrBits.W)
384    val ctr = UInt(8.W) // layer of nested call functions
385  }
386  val ras = RegInit(VecInit(Seq.fill(RasSize)(0.U.asTypeOf(rasEntry()))))
387  val sp = Counter(RasSize)
388  val rasTop = ras(sp.value)
389  val rasTopAddr = rasTop.retAddr
390
391  // get the first taken branch/jal/call/jalr/ret in a fetch line
392  // brTakenIdx/jalIdx/callIdx/jalrIdx/retIdx/jmpIdx is one-hot encoded.
393  // brNotTakenIdx indicates all the not-taken branches before the first jump instruction.
394  val brIdx = inLatch.btb.hits & Cat(io.predecode.bits.fuTypes.map { t => ALUOpType.isBranch(t) }).asUInt & io.predecode.bits.mask
395  val brTakenIdx = LowestBit(brIdx & inLatch.tage.takens.asUInt, FetchWidth)
396  val jalIdx = LowestBit(inLatch.btb.hits & Cat(io.predecode.bits.fuTypes.map { t => t === ALUOpType.jal }).asUInt & io.predecode.bits.mask, FetchWidth)
397  val callIdx = LowestBit(inLatch.btb.hits & io.predecode.bits.mask & Cat(io.predecode.bits.fuTypes.map { t => t === ALUOpType.call }).asUInt, FetchWidth)
398  val jalrIdx = LowestBit(inLatch.jbtac.hitIdx & io.predecode.bits.mask & Cat(io.predecode.bits.fuTypes.map { t => t === ALUOpType.jalr }).asUInt, FetchWidth)
399  val retIdx = LowestBit(io.predecode.bits.mask & Cat(io.predecode.bits.fuTypes.map { t => t === ALUOpType.ret }).asUInt, FetchWidth)
400
401  val jmpIdx = LowestBit(brTakenIdx | jalIdx | callIdx | jalrIdx | retIdx, FetchWidth)
402  val brNotTakenIdx = brIdx & ~inLatch.tage.takens.asUInt & LowerMask(jmpIdx, FetchWidth)
403
404  io.out.bits.redirect := jmpIdx.orR.asBool
405  io.out.bits.target := Mux(jmpIdx === retIdx, rasTopAddr,
406    Mux(jmpIdx === jalrIdx, inLatch.jbtac.target,
407    Mux(jmpIdx === 0.U, inLatch.pc + 32.U, // TODO: RVC
408    PriorityMux(jmpIdx, inLatch.btb.targets))))
409  io.out.bits.instrValid := Mux(jmpIdx.orR, LowerMask(jmpIdx, FetchWidth).asTypeOf(Vec(FetchWidth, Bool())), Fill(FetchWidth, 1.U(1.W))).asTypeOf(Vec(FetchWidth, Bool()))
410  io.out.bits.btbVictimWay := inLatch.btbPred.bits.btbVictimWay
411  io.out.bits.predCtr := inLatch.btbPred.bits.predCtr
412  io.out.bits.btbHitWay := inLatch.btbPred.bits.btbHitWay
413  io.out.bits.tageMeta := inLatch.btbPred.bits.tageMeta
414  //io.out.bits._type := Mux(jmpIdx === retIdx, BTBtype.R,
415  //  Mux(jmpIdx === jalrIdx, BTBtype.I,
416  //  Mux(jmpIdx === brTakenIdx, BTBtype.B, BTBtype.J)))
417  val firstHist = inLatch.btbPred.bits.hist(0)
418  // there may be several notTaken branches before the first jump instruction,
419  // so we need to calculate how many zeroes should each instruction shift in its global history.
420  // each history is exclusive of instruction's own jump direction.
421  val histShift = Wire(Vec(FetchWidth, UInt(log2Up(FetchWidth).W)))
422  val shift = Wire(Vec(FetchWidth, Vec(FetchWidth, UInt(1.W))))
423  (0 until FetchWidth).map(i => shift(i) := Mux(!brNotTakenIdx(i), 0.U, ~LowerMask(UIntToOH(i.U), FetchWidth)).asTypeOf(Vec(FetchWidth, UInt(1.W))))
424  for (j <- 0 until FetchWidth) {
425    var tmp = 0.U
426    for (i <- 0 until FetchWidth) {
427      tmp = tmp + shift(i)(j)
428    }
429    histShift(j) := tmp
430  }
431  (0 until FetchWidth).map(i => io.out.bits.hist(i) := firstHist << histShift(i))
432  // save ras checkpoint info
433  io.out.bits.rasSp := sp.value
434  io.out.bits.rasTopCtr := rasTop.ctr
435
436  // flush BPU and redirect when target differs from the target predicted in Stage1
437  io.out.bits.redirect := !inLatch.btbPred.bits.redirect ^ jmpIdx.orR.asBool ||
438    inLatch.btbPred.bits.redirect && jmpIdx.orR.asBool && io.out.bits.target =/= inLatch.btbPred.bits.target
439  io.flushBPU := io.out.bits.redirect && io.out.valid
440
441  // speculative update RAS
442  val rasWrite = WireInit(0.U.asTypeOf(rasEntry()))
443  rasWrite.retAddr := inLatch.pc + OHToUInt(callIdx) << 2.U + 4.U
444  val allocNewEntry = rasWrite.retAddr =/= rasTopAddr
445  rasWrite.ctr := Mux(allocNewEntry, 1.U, rasTop.ctr + 1.U)
446  when (io.out.valid) {
447    when (jmpIdx === callIdx) {
448      ras(Mux(allocNewEntry, sp.value + 1.U, sp.value)) := rasWrite
449      when (allocNewEntry) { sp.value := sp.value + 1.U }
450    }.elsewhen (jmpIdx === retIdx) {
451      when (rasTop.ctr === 1.U) {
452        sp.value := Mux(sp.value === 0.U, 0.U, sp.value - 1.U)
453      }.otherwise {
454        ras(sp.value) := Cat(rasTop.ctr - 1.U, rasTopAddr).asTypeOf(rasEntry())
455      }
456    }
457  }
458  // use checkpoint to recover RAS
459  val recoverSp = io.redirectInfo.redirect.rasSp
460  val recoverCtr = io.redirectInfo.redirect.rasTopCtr
461  when (io.redirectInfo.valid && io.redirectInfo.misPred) {
462    sp.value := recoverSp
463    ras(recoverSp) := Cat(recoverCtr, ras(recoverSp).retAddr).asTypeOf(rasEntry())
464  }
465
466  // roll back global history in S1 if S3 redirects
467  io.s1RollBackHist := Mux(io.s3Taken, PriorityMux(jmpIdx, io.out.bits.hist), io.out.bits.hist(0) << PopCount(brIdx & ~inLatch.tage.takens.asUInt))
468  // whether Stage3 has a taken jump
469  io.s3Taken := jmpIdx.orR.asBool
470}
471
472class BPU extends XSModule {
473  val io = IO(new Bundle() {
474    // from backend
475    // flush pipeline if misPred and update bpu based on redirect signals from brq
476    val redirectInfo = Flipped(new RedirectInfo)
477
478    val in = new Bundle { val pc = Flipped(Valid(UInt(VAddrBits.W))) }
479
480    val btbOut = ValidIO(new BranchPrediction)
481    val tageOut = ValidIO(new BranchPrediction)
482
483    // predecode info from icache
484    // TODO: simplify this after implement predecode unit
485    val predecode = Flipped(ValidIO(new Predecode))
486  })
487
488  val s1 = Module(new BPUStage1)
489  val s2 = Module(new BPUStage2)
490  val s3 = Module(new BPUStage3)
491
492  s1.io.redirectInfo <> io.redirectInfo
493  s1.io.flush := s3.io.flushBPU || io.redirectInfo.flush()
494  s1.io.in.pc.valid := io.in.pc.valid
495  s1.io.in.pc.bits <> io.in.pc.bits
496  io.btbOut <> s1.io.s1OutPred
497  s1.io.s3RollBackHist := s3.io.s1RollBackHist
498  s1.io.s3Taken := s3.io.s3Taken
499
500  s1.io.out <> s2.io.in
501  s2.io.flush := s3.io.flushBPU || io.redirectInfo.flush()
502
503  s2.io.out <> s3.io.in
504  s3.io.flush := io.redirectInfo.flush()
505  s3.io.predecode <> io.predecode
506  io.tageOut <> s3.io.out
507  s3.io.redirectInfo <> io.redirectInfo
508}